Synchronizing code with ADCCLK in STM32F746

[RBack.1]

My goal is to start ADC conversions a deterministic amount of time after raising a GPIO.

Since the ADC clock is slower than the instruction clock, the instruction to set SWSTART can occur in between ADC clock cycles. I currently have the ADC clock set to fPCLK2/2 and PCLK to HCLK/2, so I see up to 3 instruction cycles of jitter between raising the GPIO and starting the samples. Is there a technique useful for eliminating this jitter?

[RBack.1]

I only use two pins at a time, but they can all be used to generate the signal. The pattern is to raise one first, then the other, and start listening to the ADC a fixed period after raising the first pin. The ADC results come back on PA1 or PA2.

[waclawek.jan]

Even if not all, many of those pins are outputs of timers.

The "standard" way to have better timing without direct timer pin is to use the timer to trigger DMA from memory to GPIO to toggle the pin. However, DMA is no magic and achieving system-clock precision means to have deep understanding of what may go wrong. Using multiple pins makes this just harder.

Honestly I don't understand how did you pull out only 3 ticks jitter, especially on 'F7. I would also like to know, how exactly did you measure this jitter.

As a quick test, you can try to sync whatever code you have for this, with the ADC, by reading any ADC register immediately before this process.

JW

[RBack.1]

I use a function generator to send a signal to my ADC when triggered by the pulses on my GPIO. I calculate the phase shift from the ADC results which are between 1 and 3 integer multiples of the system clock. This makes sense since my system clock is 1/4 of the ADC clock.

I had much more jitter than this before, but by running code in ITCM with my variables in DTCM the execution is much more deterministic. The measurements show I only have 1-3 system clock periods of jitter left.

I tried doing dummy reads of the ADC to synchronize but the loops to check the ADC flags introduced cycles of variation. I think executing in an interrupt synchronized to the ADC might be necessary as gross as that seems. ISR latency is not important in this application. I just need the measurements to be made deterministically.