STM32U575ZIT6 microcontroller - issue when configuring PLL1 as the clock source

[OTM98]

Hello forum members,

I am currently working on a custom PCB based on the STM32U575ZIT6 microcontroller. I've encountered an issue when configuring PLL1 as the clock source – the code generates a hard fault. However, when selecting HSI or HSE as the source, everything works fine. The challenge is that I am unable to achieve the desired 160MHz clock speed without using the PLL.

I've observed that in the RCC (Reset and Clock Control) section, when I choose HSE or HSI, the regulator_voltage_scale is set to level 4. Interestingly, manually changing it to levels 3, 2, or 1 results in a hard fault.

I would appreciate any insights or suggestions regarding this issue. Has anyone encountered a similar problem with PLL1 configuration on the STM32U575ZIT6, or does anyone have recommendations on resolving hard faults related to clock configuration?

Thank you in advance for your assistance.

Best regards,

[TDK]

> custom PCB based on the STM32U575ZIT6

Sounds like a power issue. Do you have a nucleo board or other known good hardware you can test your code on?

Perhaps share a schematic, or check for the usual things:

• VDD/VDDA all powered and decoupled.
• VCAP all decoupled and showing valid voltage.
• VSS/VSSA all connected to GND.
• Sufficient VDD bulk capacitance.

[OTM98]

Hello,

Thank you for your input. I've checked the power supply using STM32CubeProgrammer, and the voltage reads at 3.28V. Additionally, I've tested the code on a Nucleo-U575ZI-Q board where everything functions as expected. However, on my custom PCB, I'm encountering difficulties manipulating PLL1.

Despite these measures, the issue persists on my custom PCB. I appreciate any further suggestions or insights into potential areas I should investigate.

Thank you for your assistance. 

Best regards,

 

 

[TDK]

Do you have any decoupling caps? Typically a 0.1 uF at each VDD pin.

Hardware design guide:

https://www.st.com/resource/en/application_note/an5373-getting-started-with-stm32u5-mcu-hardware-development-stmicroelectronics.pdf

[OTM98]

Thank you for your response. Yes, I have incorporated decoupling capacitors into the design. Specifically, I have placed 10 uF capacitors at each VDD pin, following the recommended practice.

For a visual reference, I've connected them as illustrated in the attached image:

 

[TDK · Accepted solution]

I see a single 10 uF capacitor in your design. This is a bulk capacitor, not a decoupling capacitor, and serves a similar but different purpose. Please refer to the hardware design guide.

The lack of decoupling capacitors can result in the hard fault you are seeing at higher clock speeds.

[OTM98]

Thank you for pointing that out and providing valuable insight into the capacitor setup.

I'm wondering if there's a solution you might suggest considering the PCB has already been fabricated. Is there a way to address this issue without significant changes to the existing PCB layout?

[FBL]

Hello @OTM98 

The issue is more likely to be linked to hardware and doesn't seem to be coverable by software. Your can refer to the documentation provided by @TDK. Also, in AN2867 more tips for oscillator PCB design may be helpful. 

[TDK]

Depends on your tools and skills at rework. I could certainly add 0.1 uF caps at each pin given sufficient motivation, though I wouldn't want to. Not realistic if you just have a hobby soldering setup.

Barring that, use lower clock speeds.