STM32U575 incorrect timing

[NuclearChips]

I am testing the functions of STM32U575 and found the following issue.

I simply wrote this in main():

while(1){
  for(i=0;i<160;i++);
  HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_11);
}

where i is defined as uint32_t.

HCLK is set to 160MHz by using PLLCLK with source=16MHz HSE, M=1, N=10, and R=1. Therefore the Cortex System timer is also 160MHz.

But I found the PC11 pin toggles at a cycle of about 17.2us with ICACHE on and about 45us with ICACHE off, instead of about 1us expected. DCACHE is always on.

I tried changing the Cortex System timer frequency but found it has completely no effect on the toggling frequency.

I have also enabled TIM2 and generated a PWM which performs correctly, showing that HSE is working correctly.

Why did this issue occur and how to solve it?

Thanks in advance.

[BarryWhit]

If you're trying for high-frequency waveform generation, software control of GPIO is a bad way to do it.

With any optimizations turned on, the compiler would likely remove the for loop as having no side-effects. At the very least, you should look at the disassembly to see what code is being generated.

If compiler optimizations are off, don't expect your code to perform well.

GPIO drive strength can be controlled via registers. Their reset value puts them at the weakest value possible. Depending on what the pin's load looks like, that can mean slow rise/fall times. But I would expect 1Mhz to be fine even with default setting.

As a general debugging approach, start at 1Hz, then gradually increase the toggle rate to find the range where code and reality being to diverge. Investigate from there.