2026-01-08 1:31 AM - last edited on 2026-01-08 3:29 AM by Andrew Neil
Hi everyone,
I’m using an STM32L562 MCU and outputting LSE (32.768 kHz) to MCO for measurement.
In LSE crystal mode, I see a large frequency deviation on the oscilloscope (much larger than expected ppm-level error).
To rule out the crystal itself, I checked the 32.768 kHz crystal and it seems OK.
Then I tried LSE bypass mode (feeding an external 32.768 kHz clock into the LSE pins). In this case, the MCO output frequency error becomes very small, and the waveform/frequency looks correct.
So I suspect there might be an issue with the LSE oscillator circuit (load caps, PCB layout, drive strength, leakage, etc.) when running in crystal mode.
Questions:
Has anyone experienced large LSE frequency error in crystal mode on STM32L562 / STM32L5 series?
Any common root causes (wrong load capacitors, stray capacitance, drive level, board leakage, etc.)?
Any recommended debugging steps or configuration tips (e.g., LSE drive settings, oscillator startup behavior, measurement method, etc.)?
Thanks in advance!
Here is my test code :
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
{
Error_Handler();
}
HAL_PWR_EnableBkUpAccess();
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI
|RCC_OSCILLATORTYPE_LSE
|RCC_OSCILLATORTYPE_LSI;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; // 48 MHz on L5
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.LSIDiv = RCC_LSI_DIV1;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
/* We no longer need PLL as system clock */
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
HAL_RCCEx_EnableMSIPLLMode();
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK |
RCC_CLOCKTYPE_SYSCLK|
RCC_CLOCKTYPE_PCLK1 |
RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // HCLK = 48 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // PCLK1 = 48 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // PCLK2 = 48 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
Error_Handler();
}
// __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI);
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_LSE, RCC_MCODIV_1);
//HAL_RCCEx_EnableLSCO(RCC_LSCOSOURCE_LSE);
}Edited to apply source code formatting - please see How to insert source code for future reference.
2026-01-08 1:56 AM
Welcome to the forum.
Please see How to write your question to maximize your chances to find a solution for best results.
Also: How to insert source code
In particular, please give details of your hardware setup (schematics, etc), tools, etc.
It would be better to use your scope's image download facility - then you won't get all the blur, reflections, unwanted background, etc of a photograph.
@Jerry_Cao wrote:Here is my test code
Is that from CubeMX, or manually written?
2026-01-08 3:05 AM - edited 2026-01-08 3:05 AM
Hello @Jerry_Cao and welcome to the ST community,
Did you refer to the application note: AN2867 "Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs" / section "3.7 Crystal pullability" ? It could be linked to the CL capacitance.
2026-01-08 3:25 AM
Almost the same discussion here.
2026-01-08 5:25 AM - edited 2026-01-08 5:25 AM
> To rule out the crystal itself, I checked the 32.768 kHz crystal and it seems OK.
How exactly did you do this? Just look at it and say "yep, that's a crystal"?