stm32l452, uart, when TXE = 1 ?

[bso]

stm32l452, uart. CR1_TE is = 1, now I set CR1_TXEIE = 1. Is ISR-TXE = 1 (and INT generated) now too? Or really only if 'data is transferred to the shift register' ?

[S.Ma]

      LL_USART_DeInit(USART3);      
      LL_USART_StructInit(&USART_InitStruct);
      USART_InitStruct.BaudRate = bps;
      Error = LL_USART_Init(USART3, &USART_InitStruct);
      LL_USART_SetTXRXSwap(USART3, swap_rx_tx ? LL_USART_TXRX_SWAPPED : LL_USART_TXRX_STANDARD); // 
      LL_USART_Enable(USART3);
      NVIC_SetPriority(USART3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0x0F, 0x00));
      NVIC_EnableIRQ(USART3_IRQn);
      LL_USART_EnableIT_RXNE(USART3);
      if(BV_from_SPIP[STM_SERIAL].bCount)// Dynamic case: we activate the TX if the BV_from_SPIP is already not empty (or we flush it)
        LL_USART_EnableIT_TXE(USART3);
 
==============
void USART3_IRQHandler(void)
{
  uint8_t byte;
  /* USER CODE BEGIN USART3_IRQn 0 */
  if (LL_USART_IsEnabledIT_RXNE(USART3)&&(LL_USART_IsActiveFlag_RXNE(USART3))) { // RNXEbyte received by USART
    byte = LL_USART_ReceiveData8(USART3); // if you want to distribute this data, try to do so outside this IRQ handler. Use the FIFO for it if possible
    AddToBV(&BV_to_SPIP[STM_SERIAL], byte);
  }
  
  if (LL_USART_IsEnabledIT_TXE(USART3)&&(LL_USART_IsActiveFlag_TXE(USART3))) { // TXE byte ready to send by USART
    byte = ClipBV_Down(&BV_from_SPIP[STM_SERIAL]); // if you want to distribute this data, try to do so outside this IRQ handler. Use the FIFO for it if possible
    LL_USART_TransmitData8(USART3, byte);
  }
  /* USER CODE END USART3_IRQn 0 */
  /* USER CODE BEGIN USART3_IRQn 1 */
 
  /* USER CODE END USART3_IRQn 1 */
}
 

BV is a SW FIFO to transit data between USART and application paces

BV has built-in callback to stop IT for TX when empty and enable IT for TX when no longer empty.

[Tesla DeLorean]

It will generate an interrupt whenever the bit is high. It will be high when the holding register is empty. It will be low when the shift register is busy, and the holding register is full. It will transition from low to high as the holding register moves to the shift register.