STM32L051 ADC clockrate discrepancy

ADC_CLOCKPRESCALER_PCLK_DIV1 is the obsolete definition, use ADC_CLOCK_SYNC_PCLK_DIV1 instead.

Using that value has a limitation, maybe you hit it. Here is a copy-paste from the reference manual (RM0377) [Click Show More]

13.12.5 ADC configuration register 2 (ADC_CFGR2)

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Bits 31:30 CKMODE[1:0]: ADC clock mode

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11: PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle)

It is not obsolete if you do not use the new library.

I will not be porting everything over since the new defs do not provide anything new, just renames.

I did see this limitation and I am indeed running 50% duty cycle.

All domains are running 32 MHz.

OK, what about this:

Datasheet:

6.3.15 12-bit ADC characteristics

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fADC | ADC clock frequency, Voltage scaling Range 1 | Max: 16MHz

Dangit... I missed that one. Looked and looked.

You're right. I am overdriving the ADC and it seems to then perform at a bit less. May be bus-related?

It is doing a good job though.

I redid my test with 16 MHz clock input (PCLK/2) and 71.5 cycles sampling time.

I now use 12 channels, 8x oversampling and still the DMA transfer, sampling in reverse order.

Result is 1812 Hz samplerate using the "floating adc pin trick" to record on the oscilloscope the actual sample and hold bursts on the pin. This is 16 MHz / (8 * 12 * 1812) = 91.979 cycles per sample-cycle.

It seems I am loosing 8 cycles. I wondered if this is the 8 cycles needed by the sums in the adc oversampling so I set it to 16x oversampling.

Result was 905.8 Hz which fits very well with the previous test: 16 MHz / (16 * 12 * 905.8) = 91.9997 cycles per sample-cycle.

So, 8 cycles extra. I can't find this anywhere in the docs.

If I had the DMA do triggering to the ADC there would be latency I guess, but I use free running mode.