2016-10-13 05:38 AM
A quick scan of my STM32Cube_FW_L0_V1.7.0 directory shows:
Search ''HSI48ON'' (2894 hits in 1042 files) C:\Users\PD\STM32Cube\Repository\STM32Cube_FW_L0_V1.7.0\Drivers\CMSIS\Device\ST\STM32L0xx\Include\stm32l052xx.h (5 hits) Line 3609: &sharpdefine RCC_CRRCR_HSI48ON_Pos (0U) Line 3610: &sharpdefine RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */ Line 3610: &sharpdefine RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */ Line 3611: &sharpdefine RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */ Line 3611: &sharpdefine RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */...It seems that the STM32L0 sample code was copied from a different family.Is it safe to replace all 2894 typos automatically ?Is this just a cosmetic problem or a sign of poor quality control ?Can the STM32L0 HAL and Low-layer drivers be trusted ?Peter #stm32l0-hsi482016-10-13 06:45 AM
Hi Peter,
This is not a bug: in fact the STM32L0x2 and STM32L0x3 devices embed an internal 48 MHz RC oscillator (HSII48) dedicated to provide a high precision clock to USB and random number generator (RNG)Please refer to Reset and clock control (RCC) section in the RM0376 Reference manual (for stm32l052xx device).-Syrine-2016-10-18 06:58 AM
Hi Syrine,
Thank you for pointing me to the RM0376 Reference manual (for stm32l052xx device).This reference clarified the nature of the problem.The confusion started with the STM32L011K4-Nucleo example for ADC in STM32Cube_FW_L0_V1.7.0.There in system_stm32l0xx.c SystemInit is a line of code : RCC->CRRCR &= (uint32_t)0xFFFFFFFE; /*!< Reset HSI48ON bit */The STM32L0x1 reference manual RM0377 does not mention anything about CRRCR register or HSI48ON bit.The sample code should not clean compile for STM32L011K4 target.Peter