STM32L unstable at high frequencies

mailmail9117 · ‎2012-12-10

Posted on December 11, 2012 at 02:23

My STM32L151RCT seems to become unstable when I set the SYSCLK to PLL=26MHZ.

Lower frequencies (say, 20MHZ) appear to be solid. The failure mode is inconstantly a HardFault, or stack pointer gets corrupted after a few minutes of operation. It's a little hard to tell because the debugger loses its marbles. I am setting the VCORE to 1.8V using

RCC->APB1ENR |= RCC_APB1ENR_PWREN;
 PWR->CR = PWR_CR_VOS_0;

while((PWR->CSR & PWR_CSR_VOSF) != RESET);

PLL settings are HSE=20MHZ, RCC_PLLMul_4, RCC_PLLDiv_3 I'm pretty sure SYSCLK is actually 20MHZ when it works and 26MHZ when it doesn't because I can output a fraction of it on the MCO pin and measure with a scope. The VDD pin measures 3.3V. In the datasheet I don't see anything I must do to operate at high frequencies other than setting VCORE. It looks to me like PCLK HCLK and Flash wait states can be anything. Is there some required setting I am missing? DP #vcore-stm32l-pll-sysclk

Tesla DeLorean · ‎2012-12-10

Posted on December 11, 2012 at 03:30

The reference manual discusses voltage and frequency, and how it relates to flash wait states, and prefetch unit. Definitely going to need at least 1 WS @ 26 MHz. ST talks about 16 MHz, but flash in other models is rated at 24 MHz

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..

mailmail9117 · ‎2012-12-11

Posted on December 11, 2012 at 20:37

Clive,

The Flash wait states was already set at 1, but you pointed me to exactly the right section in the manual. It works when flash is set to use 64 bit accesses. The requirement that I appear to have been violating is that 32 bit accesses requires WS to be set to 0.

Thanks!!

DP