STM32H755 WWDG interrupts

[iTTy]

Hy every one,
I'm facing up the WWDG usage on a STM32H755 MCU.
I noticed that WWDG peripheral has 2 interrupts: normal one and the early wake-up EWI one.
What is the difference?
Manual is not clear!

Thanks in advance

[Pavel A.]

What is the "normal" interrupt? where have you seen it?

[AScha.3 · Accepted solution]

Hi,

manual is ok.

The "normal" action is on counting down to 0x3F -> reset cpu.

Just, if enabled, at 0x40 you get the early wake-up INT : now you can decide, to stop/prevent the reset for now, by writing/reload the WWDG counter; maybe a time consuming action, like writing to a sd-card, needs unknown millisecs more, so by using a flag you can stop the WWDG reset for some time; after this is finished, clear your flag and dont write the WWDG counter, so it will reset the cpu, if no reload the WWDG counter happens in time.

So the early wake-up INT can be the (only) way, to stop the WWDG - if you need this.

[iTTy]

@Pavel A. and @AScha.3 , thanks for yours reply.

Regarding the two interrupt:

this one is the "normal" one, which is also reported in the NVIC1 section.

this is the EWI.

@AScha.3 , so these interrupts basically differ for 1 count, right?
But with the NVIC one reset has already been initiated, there are other functional differences?
If I just need to set a variable for WWDG detection (after reset), could I use this one.

[AScha.3]

>so these interrupts basically differ for 1 count, right?

Right.  But the early is just an INT , the "normal" is reset/restart.

> If I just need to set a variable for WWDG detection (after reset), could I use this one.

What to detect then ?

[iTTy]

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@AScha.3 wrote:

> If I just need to set a variable for WWDG detection (after reset), could I use this one.

What to detect then ?

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I would like to recognize the reset cause: after WWDG reset the system shall enter in error state; otherwise (power on reset or bootloader jump) it shall start normally.

It could be useful the trick to freeze the WWDG, but this is probably off-topic there...

Thanks again for your reply!

[AScha.3]

>I would like to recognize the reset cause:

For this : see rm,  there is a extra register...

[iTTy]

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@AScha.3 wrote:

..."so by using a flag you can stop the WWDG reset for some time; after this is finished, clear your flag and dont write the WWDG counter, so it will reset the cpu, if no reload the WWDG counter happens in time.

So the early wake-up INT can be the (only) way, to stop the WWDG - if you need this."

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Actually I would like to do something like this (external SPI EEPROM save).

@AScha.3 : the flag you wrote about, is the EWIF?

[AScha.3]

No, its something like a global variable, you use to block/stop the WWD from resetting the system.

So in the "Early wakeup INT" you check the flag, if its on "1" or whatever you define, ok, then block WWD by giving now write the watchdog and return from INT. Same...as long, as flag is active. If flag zero, do nothing, return from INT.

Then watchdog will on next cycle reset the system.

OK?

[iTTy]

@AScha.3 ,

thaks for your advice!

I did as you suggested and it works: simply and effective!

Sorry if my question seemed st**id, but I'm used on other platforms where WDG shall/can be managed only through its own registers and it is possible to stop it...

Thanks again!