STM32H755 Reset Reason

[scuba]

Hello,

I am using an STM32H755 dual core chip and occasionally, our reset reason (RCC_RSR) is decoding to have only the

D1RSTF bit and D2RSTF bit set.  Per the documentation, it does not seem this is an expected combination alone...

Per table 56 in section 9.4.4, seems only valid reasons with either of those bits set are:

(doc I am referring to is the ref_manual_rm0399-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics-2.pdf)

Power-on reset (pwr_por_rst) - but this should have an additional 3 bits (PORRSTF, PINSTF, and BORRSTF bits)

D1 exits DStandby mode - but this should only have D1RSTF  set  (and, not using standby currently)

D2 exits DStandby mode - but this should only have D2RSTF  set (and again, not using standby currently)

Am I misinterpreting the table? 

Any other thoughts?

thanks,

-mike

[Sarra.S]

Hello @scuba, 

Your interpretations of the table are correct 

According to RM: " To prevent critical applications from mistakenly entering a low-power mode, two low-power
mode security resets are available. When enabled through nRST_STOP_C[2:1] option bytes

* D1 domain and/or D2 accidentally enters DStandby mode. This type of reset is enabled by resetting nRST_STDBY_D[2:1] user option bytes. In this case, whenever a domain D1 or D2 DStandby mode entry sequence is successfully executed, a system reset is generated."

This might be the case for you maybe? 

Also, as you are not using low-power modes, your code might be writing to reserved bits in registers that could lead to an undefined behavior... These are just assumptions as there are no details or context in your question.