Hi all
For some reason unknown to me, my PHYSEL bit in GUSBCFG is not setting, and I don't know why
static inline void core_initialisation(void) //from page 3403
{
// 1. Program OTG_GAHBCFG register:
// - Enable global interrupt mask bit (GINTMSK)
// - Enable Rx FIFO non-empty interrupt (RXFLVL)
// - Set periodic Tx FIFO empty level (PTXFELVL)
// Enable global interrupt (GINT)
SET_BIT(USB_OTG_HS->GAHBCFG, USB_OTG_GAHBCFG_GINT);
// Enable Rx FIFO non-empty interrupt mask
SET_BIT(USB_OTG_HS->GAHBCFG, USB_OTG_GAHBCFG_PTXFELVL); // periodic Tx FIFO empty level
// Note: RXFLVL interrupt is unmasked in GINTMSK, not GAHBCFG.
// 2. Program OTG_GUSBCFG register:
// - Set full-speed device mode (FDMOD)
// - Select embedded PHY (PHYSEL)
// - Set turnaround time (TRDT)
MODIFY_REG(USB_OTG_HS->GUSBCFG,
USB_OTG_GUSBCFG_FDMOD | USB_OTG_GUSBCFG_PHYSEL | USB_OTG_GUSBCFG_TRDT,
USB_OTG_GUSBCFG_FDMOD | USB_OTG_GUSBCFG_PHYSEL | _VAL2FLD(USB_OTG_GUSBCFG_TRDT, 0x09)
);
// 3. Unmask interrupts in OTG_GINTMSK register:
SET_BIT(USB_OTG_HS->GINTMSK,
USB_OTG_GINTMSK_USBRST | // USB reset interrupt mask
USB_OTG_GINTMSK_ENUMDNEM | // Enumeration done interrupt mask
USB_OTG_GINTMSK_SOFM | // Start of frame mask
USB_OTG_GINTMSK_USBSUSPM | // USB suspend mask
USB_OTG_GINTMSK_WUIM | // Wakeup interrupt mask
USB_OTG_GINTMSK_IEPINT | // IN endpoint interrupt mask
USB_OTG_GINTMSK_OEPINT | // OUT endpoint interrupt mask
USB_OTG_GINTMSK_RXFLVLM // Rx FIFO non-empty mask
);
// Optional: read CMOD bit from GINTSTS to check mode (device or host)
// uint32_t mode = READ_BIT(USB_OTG_HS->GINTSTS, USB_OTG_GINTSTS_CMOD);
// if(mode == USB_OTG_GINTSTS_CMOD) { /* Host mode */ } else { /* Device mode */ }
}
static void initialise_device_core() //FROM PAGE 3405
{
core_initialisation();
HAL_Delay(50);
// Enables the clock for USB core.
SET_BIT(RCC->AHB2ENR1, 1<<14|1<<15);
SET_BIT(USB_OTG_HS->GCCFG, USB_OTG_GCCFG_PDEN|USB_OTG_GCCFG_PULLDOWNEN|USB_OTG_GCCFG_VBVALEXTOEN|USB_OTG_GCCFG_VBVALOVAL|USB_OTG_GCCFG_SDEN|USB_OTG_GCCFG_DCDEN|1<<16|1<<18);
// Configures the device to run in full speed mode.
MODIFY_REG(USB_OTG_HS_DEVICE->DCFG,
USB_OTG_DCFG_DSPD,
_VAL2FLD(USB_OTG_DCFG_DSPD, 0x03)
);
// Enables VBUS sensing device.
SET_BIT(USB_OTG_HS->GCCFG, USB_OTG_GCCFG_VBDEN);
// Unmasks the main USB core interrupts.
CLEAR_BIT(USB_OTG_HS_DEVICE->DCTL, USB_OTG_DCTL_SDIS );
// Clears all pending core interrupts.
WRITE_REG(USB_OTG_HS->GINTSTS, 0xFFFFFFFF);
// Unmasks transfer completed interrupts for all endpoints.
SET_BIT(USB_OTG_HS_DEVICE->DOEPMSK, USB_OTG_DOEPMSK_XFRCM);
SET_BIT(USB_OTG_HS_DEVICE->DIEPMSK, USB_OTG_DIEPMSK_XFRCM);
if (USB_OTG_HS_GLOBAL->GINTSTS & USB_OTG_GINTSTS_USBRST)
{
log_info("Setup bs is done.");
}
}
I have set my phy sel to happen early on, but its still not working.
Any thoughts would be appreciated
