STM32H755 dual ADC DMA sample rate is half

[mosamasa]

Hi,

I'm using STM32H755 nucleo board and evaluating ADC. I'm using ADC1 and ADC2. I like to get 1.92MSPS per ADC (12bit). According to my understanding I need minimum 8 cycles for conversion and therefor I was using 15.36MHz clock rate. With these settings, I'm getting 960kSPS rate, which is half what I expected. Then I doubled clock rate to 30.72MHz, which gives correct 1.92MSPS per ADC. According to AN5354, maximum ADC frequency is 17MHz (LQFP144), which is much lower than my current setting. Can I use 30.72MHz clock for ADC and why it has to be double?

[CMYL]

Hello @mosamasa 

Regarding the sampling rate, the ADC needs a minimum of 2.5 ADC clock cycles for the sample period and 12.5 ADC clock cycles for conversion (12-bit resolution), resulting in a total of 15 ADC clock cycles. This aligns with your observation that doubling the clock rate to 30.72 MHz achieves the desired 1.92 MSPS per ADC.

If you can share more details on the ADCs settings or a code snippet as you are using DMA which probably triggered by Timer?

Best regards

[MasterT]

Get RM0399, I think there is a divider /2 in the ADC clock interface, same as on H743 /753 adc  version V.