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STM32H753VIT6 SD-card SDR104

tyassin
Associate III

Hi,

I would like to use this device: STM32H753VIT6 to communicate withan SD-card in SDR104 mode.

As I understand it would require an I/O voltage on the card side of 1.8V. This is where I become insecure if the given device can generate this voltage internally or I need a voltage translator?

Thank you

1 ACCEPTED SOLUTION

Accepted Solutions

Ok, dug harder and found the 8-bit DDR. I think this might have been a Kingston device, the H750-DK was a physically slower part (got ~33MBps ceiling). Measuring time with DWT CYCCNT, cross checking is millisecond SysTick in case the cycle counter wrapped.

..
CRC32 A534026F Memory Image
32768000 Bytes, 477729376 Cycles
27.44 MBps Write (FatFs)
1194 ms run time
27.44 MBps (Sanity Check)
24008628 24008640  2048 COUNTER.002
................................
CRC32 A534026F PKZIP 5ACBFD90 COUNTER.002
32768000 Bytes, 487373292 Cycles
26.89 MBps Write (FatFs)
1219 ms run time
26.88 MBps (Sanity Check)
24008628 24008640  2048 COUNTER.002
................................
CRC32 A534026F PKZIP 5ACBFD90 COUNTER.002
COUNTER.002
32768000 Bytes, 210764901 Cycles
62.19 MBps Read (FatFs)
527 ms run time
62.18 MBps (Sanity Check)
32768000 Bytes, 210747061 Cycles
62.19 MBps Read (FatFs)
527 ms run time
62.18 MBps (Sanity Check)
Done!
PLL1_Q_CK=200000000, 200.00 MHz
PLL2_R_CK=        0,   0.00 MHz
SDMMC1_CK         2,  50.00 MHz
 8-bit DDR
Infinite Loop...  Press R to Restart

 

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View solution in original post

8 REPLIES 8
FBL
ST Employee

Hello @tyassin 

 

First UHS-I SDR104 mode is supported. During power on and initialization, by sending CMD1 you check the match between card operating voltage and the target as detailed in AN5200.

According to RM0433 section 55.8 Ultra-high-speed phase I (UHS-I) voltage switch, the signal voltage level is supported through an external voltage translation transceiver like STMicroelectronics ST6G3244ME.

 

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

You'd need a transceiver externally, with a clock signal looped back, and a direction pin.

Pull the schematic for the original STM32H743I-EVAL board (likely under the CAD Resources tab for the product). It uses a now obsolete NXP MCM module.

I will however note that the drivers and performance probably aren't going to meet expectations. So be prepared for some work and disappointment.

Frankly the hardware lacks the bandwidth to do much useful, and without a better OS, file system and caching this is probably going to disappoint on ALL fronts. You're likely to run out of the ability to sink or source the kind of data volumes before you get close to SDR104

Benchmark your current performance with a 50 MHz and 75 MHz SD clock across the interface. Using normal SDHC voltages.

Most speed can be attained by using LARGE ALIGNED transfers to the cards, think FAT CLUSTER, or ERASE BLOCK SIZE for the underlying media. Perhaps 32KB at least. What will kill performance are lots of small, petty, fwrite() / fread() type operations.

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Up vote any posts that you find helpful, it shows what's working..
tyassin
Associate III

Hello Belaid,

Thank you for the answer. Yes I have browsed the manual afterwards and also noticed the section. Many of these translation tranceives are obsolete and the new ones mainly seem to focus on host devices operating at 1.8V....then I am not sure why the are needed?

Br.

Hello,

 

Thank you very much for the elaborate answer.
I have also noticed from other posts that this has been asked a few times, but the datasheet for the device claims it, so also the reason I asked 🙂

Can I ask what your experience is with the SD-card performance? But do I read you comment correctly, when you say I just hook up the STM32H7 directly to the SD-Card, with 3.3V?

Br. 

I've built / benchmarked systems where I've read cards faster than 30 MBps, but I think that's probably a bit contrived as it's not "doing" anything with the data.

Also worked with 8-bit eMMC DDR, perhaps approaching 40 MBps reads there with a 52 MHz clock in SDR mode

The real issue is having enough memory and bandwidth to manage, process and transform the data from the firehose. Something that honestly doesn't scale well on MCU's

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Up vote any posts that you find helpful, it shows what's working..

This was from a subsystem / benchmark app I wrote for a client last year. I built 4-bit and 8-bit DDR versions too, but it's not my hardware, so don't have the benches for those. But it was a well designed system, with a fast/performance eMMC part, and solid signal integrity.

H75x eMMC Demo

Core=415000000, 415.00 MHz
CPUID 411FC271 DEVID 450 REVID 2003
Cortex M7 r1p1
C0000038 2000B458 00000000
10110221 12000011 00000040
FPU-D Single-precision and Double-precision
STM32H7xx
HCLK=207500000
APB1=103750000
APB2=103750000
PLL1_P_CK=415000000, 415.00 MHz
PLL1_Q_CK=207500000, 207.50 MHz
PLL2_P_CK=0,   0.00 MHz
PLL2_R_CK=0,   0.00 MHz
FatFs Testing (68300)
SystemCoreClock: 415000000
APB1=103750000
APB2=103750000
   32.0 MB used
Display Directory
----   32768000 /COUNTER.002
CRC32 A534026F Memory Image
32768000 Bytes, 606929249 Cycles
22.41 MBps Write (FatFs)
1463 ms run time
22.40 MBps (Sanity Check)
20008618 20008620  2048 COUNTER.002
................................
CRC32 A534026F PKZIP 5ACBFD90 COUNTER.002
32768000 Bytes, 611379494 Cycles
22.24 MBps Write (FatFs)
1473 ms run time
22.25 MBps (Sanity Check)
20008618 20008620  2048 COUNTER.002
................................
CRC32 A534026F PKZIP 5ACBFD90 COUNTER.002
COUNTER.002
32768000 Bytes, 342069216 Cycles
39.75 MBps Read (FatFs)
824 ms run time
39.77 MBps (Sanity Check)
32768000 Bytes, 342132698 Cycles
39.75 MBps Read (FatFs)
825 ms run time
39.72 MBps (Sanity Check)
Done!
PLL1_Q_CK=207500000, 207.50 MHz
PLL2_R_CK=        0,   0.00 MHz
SDMMC1_CK         2,  51.88 MHz
 8-bit
Infinite Loop...

 

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..

Ok, dug harder and found the 8-bit DDR. I think this might have been a Kingston device, the H750-DK was a physically slower part (got ~33MBps ceiling). Measuring time with DWT CYCCNT, cross checking is millisecond SysTick in case the cycle counter wrapped.

..
CRC32 A534026F Memory Image
32768000 Bytes, 477729376 Cycles
27.44 MBps Write (FatFs)
1194 ms run time
27.44 MBps (Sanity Check)
24008628 24008640  2048 COUNTER.002
................................
CRC32 A534026F PKZIP 5ACBFD90 COUNTER.002
32768000 Bytes, 487373292 Cycles
26.89 MBps Write (FatFs)
1219 ms run time
26.88 MBps (Sanity Check)
24008628 24008640  2048 COUNTER.002
................................
CRC32 A534026F PKZIP 5ACBFD90 COUNTER.002
COUNTER.002
32768000 Bytes, 210764901 Cycles
62.19 MBps Read (FatFs)
527 ms run time
62.18 MBps (Sanity Check)
32768000 Bytes, 210747061 Cycles
62.19 MBps Read (FatFs)
527 ms run time
62.18 MBps (Sanity Check)
Done!
PLL1_Q_CK=200000000, 200.00 MHz
PLL2_R_CK=        0,   0.00 MHz
SDMMC1_CK         2,  50.00 MHz
 8-bit DDR
Infinite Loop...  Press R to Restart

 

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..
tyassin
Associate III

Thank you very much for the answers.
I have decided to continue to so see what speed we can achieve without a transciever and connecting the SD-Card directly to the MCU.