stm32h750vbt6 DMA is not working if active D cache

[A.Caliskan]

I have read previous posts ,,,I set up dma to read adc ,Although dma's destination address is allocated from AXI RAM, dma does not work when d cache is active.Can anyone share detailed information or a sample code about this?

[Tesla DeLorean]

I'm sure the DMA and D-Cache do exactly what they are supposed too. Understand how to handle Cache Coherency properly. There's a slew of CMSIS functions design for this explicit purpose. My experience is that ARM has extensively documented the function of it's MCUs