stm32h747xx linker file modifications

[massimoperdigo]

Hello everyone!

I have a quick question regarding memory allocation on an STM32H747XIHx MCU. While working with the linker file, I noticed the following memory definitions:

MEMORY {
    RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
    FLASH (rx)   : ORIGIN = 0x08000000, LENGTH = 1024K /* Memory is divided. Actual start is 0x08000000 and total length is 2048K */
    DTCMRAM (xrw): ORIGIN = 0x20000000, LENGTH = 128K
    RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
    RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
    ITCMRAM (xrw): ORIGIN = 0x00000000, LENGTH = 64K
}

As you can see, the comment indicates that the total available FLASH memory is 2048 KB, but the linker file only defines 1024 KB.

I then checked the reference manual and found that the FLASH memory spans from 0x08000000 to 0x081FFFFF, which confirms the 2048 KB size. However, when calculating the size using address boundaries (e.g., 0x080FFFFF - 0x08000000), the result is only 2023 KB, not 1024 KB as stated in the linker file. I think this is a misunderstood because I am not taking into account the last address (I should add a +1 when subtracting the boundaries, right?)

A correct approach of a linker file would be:

MEMORY {
    RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
    FLASH (rx)   : ORIGIN = 0x08000000, LENGTH = 1024K /* Memory is divided. Actual start is 0x08000000 and total length is 2048K */
    FLASH2 (rx)   : ORIGIN = 0x08100000, LENGTH = 1024K /* Memory is divided. Actual start is 0x08000000 and total length is 2048K */
    DTCMRAM (xrw): ORIGIN = 0x20000000, LENGTH = 128K
    RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
    RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
    ITCMRAM (xrw): ORIGIN = 0x00000000, LENGTH = 64K
}

Additionally, I noticed that the total RAM defined in the linker file is divided as follows:

• RAM_D1: 512 KB

• DTCMRAM: 128 KB

• RAM_D2: 288 KB

• RAM_D3: 64 KB

• ITCMRAM: 64 KB

The sum of these gives a total RAM size of 1056 KB, not the 1 MB typically mentioned in documentation. Could anyone confirm if this breakdown is correct or if I’m missing something?

Thanks in advance for your help!

[Tesla DeLorean]

There are lots of ways to validly floor-plan the available resources.

When used as a dual-core, you need to decide which core uses/manages which memories. The M4 typically starts with the assumption that it's code lives in FLASH at 0x08100000

You'll need to think more broadly about where each core situates it's HEAP, STACK and STATICS. Watch how tightly coupled the different memories are situated to each of the cores.

[STea]

Hello @massimoperdigo ,
STM32H747XIHx MCU is a dual core product, and it has dual bank feature the ideal configuration is to assign each bank to a core as demonstrated in the example if you inspect the linker files for booth core you will see that each core is getting a bank assigned to it.
Now regarding RAM sizes, you should only take into consideration what is indicated as memory boundaries for your product in the reference manual 

Regards

[SofLit]

Hello,

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@massimoperdigo wrote:

Hello everyone!

I have a quick question regarding memory allocation on an STM32H747XIHx MCU. While working with the linker file, I noticed the following memory definitions:

---

You didn't mention where you find this linker? in CubeH7?

Meanwhile, CM4 and CM7 both access the entire 2MB but for program and literal pool, you can limit the boundary as you want with the related linker file. You can even disable one core in the option byte and make the another uses the all 2M of the flash memory. 

For the SRAM, I didn't understand your point:

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@massimoperdigo wrote:

Additionally, I noticed that the total RAM defined in the linker file is divided as follows:

• RAM_D1: 512 KB

• DTCMRAM: 128 KB

• RAM_D2: 288 KB

• RAM_D3: 64 KB

• ITCMRAM: 64 KB

The sum of these gives a total RAM size of 1056 KB, not the 1 MB typically mentioned in documentation. Could anyone confirm if this breakdown is correct or if I’m missing something?

---

These SRAM sizes are correct. It's true that in the datasheet it says 1M of SRAM but indeed it's 1056kB excluding Backup SRAM. May be the wording could be "more than 1M of SRAM".