STM32H747 Dual Core (M7 + M4)

[Tesla DeLorean]

https://www.st.com/content/ccc/resource/sales_and_marketing/presentation/technology_presentation/group0/ca/b8/42/c4/e3/9f/40/2e/CES_2019_Amazon_Alexa_Home_Control/files/CES_2019_Amazon_Alexa_Home_Control.pdf/jcr:content/translations/en.CES_2019_Amazon_Alexa_Home_Control.pdf

[MikeDB]

Where do you see mention of an M4 ? Seems to be two M7s. There is however a dual A7 and M4 released the other day as well.

[Tesla DeLorean]

.

[Tesla DeLorean]

.

[AvaTar]

The H series seems to have quite a tough startup - I guess ST has underestimated the complexity, and perhaps stepped out of the designer's comfort zones.

That leaves an uneasy feeling when thinking on the STM32MP1, the A7/M4 dual core.

[Jack Peacock_2]

Freescale/NXP has been producing mixed A7/8/9 and M3/4 controllers for a while now. It's not really a new technology except for ST venturing into a market that's been dominated by the likes of NXP and TI. The A series is inherently designed for multi-core and the reference manual for the MP1 shows ST does understand what's needed in a heterogeneous mixed core environment.

The biggest surprise in the MP1 was that ST didn't go with multiple A7s (2 or 4 cores) since the support to build it is there. I suppose ST has this on the roadmap somewhere.

I'm not too sure what the value of multiple M class cores on the same IC would be. An A series core quickly becomes more economical in most cases if performance is an issue. The past attempts by some vendors (i.e. the mixed M4 and M0 cores) never really caught on. High speed interconnects like SPI work fine when a distributed app can be built from M class cores, and it avoids the flash AHB bus contention problems with multiple M cores.

Jack Peacock

[Tesla DeLorean]

Well I think the H7 silicon has been spun at least 4 times.

My worry is more of the support nightmare that multi-core is going to be for the devs who currently find putting their pants on a challenge.

[Tesla DeLorean]

M7 and M4 functionality disclosed here. Assuming released product will support M7@480MHz, M4@240MHz, M4 lives on D2, and DSI functions.

https://www.st.com/content/ccc/resource/technical/document/user_manual/group0/67/37/e1/52/3a/dc/44/33/DM00386433/files/DM00386433.pdf/jcr:content/translations/en.DM00386433.pdf