2023-12-01 07:14 AM
Hello friends,
i have the following setup:
problem:
What could be the reason for this?
I have connected the signals:
I think the error must be somewhere in the hardware.
I tested the toolchain on a Nucleo Board (STM32H723ZGT6) and all works fine there.
I you need more information on this, please let me know.
Thanks for your help.
Regards, Tim
Solved! Go to Solution.
2023-12-04 05:56 AM
You might find the hardware design guide useful as it goes over these types of things:
Note that VCAP1 and VCAP2 each need a 2.2uF to ground. Will likely work okay with just one, but it's easy enough to follow the recommendations if you're building a new board.
Pullup on NRST is not needed, just a 0.1uF to GND. Won't hurt anything.
2023-12-01 08:01 AM - edited 2023-12-01 08:16 AM
> NRST (Pin27) to +3V3
NRST should be bypassed to GND with a 0.1 uF capacitor. It should not be tied to 3.3V
(wrote the below before finding the above red flag)
If the code works on a nucleo board but not your custom board, the issue is likely the custom board and not your software configuration. Showing your schematic would be helpful, but here are the typical culprits:
Edit: PDR_ON should generally be tied to VCC unless you want to disable the regulator, which is uncommon.
2023-12-01 09:07 AM
Check voltage on VCAP pins.
On the software side, as your code WILL RUN, double check HSE_VALUE define, LDO/SMPS settings, VOS settings, PLL settings in SystemClock_Config(). Make sure you're not violating the PLL / VCO limits.
Ideally you should be able to jumper BOOT0, you want it low for normal operation, but being able to pull it High and cycle power completely a couple of times will help to establish if it's YOUR CODE breaking things.
2023-12-02 01:39 AM
Good morning,
thank you for your quick replys and the suggestions. I have attached my controller schematics below.
i have tried the following adjustments:
2023-12-02 02:08 AM - edited 2023-12-02 02:09 AM
I mean your schematics is complete wrong around SMPS and too STMLink isnt JTAG interface. Then JTAGRST is fail connected too.
Boot0 on GND was ok , but better is puldown 10k.
NRST (this connect to P400 rst) on 3V3 is fail, required is NC or pullup 10k to 3V3.
2023-12-02 06:16 AM
> Added a 0,1µF from GND to +3V3 nearby the NRST.
Sonds like NRST is still tied to 3.3V. This is still a problem as it prevents the chip from being able to reset.
2023-12-04 05:12 AM
Hello,
thank you very much for your answers.
I have made the following changes in the schematics by now:
This should work, right?
I will order a new PCB with this design, as the current one is to filigree to do these changes.
Thanks again!
2023-12-04 05:56 AM
You might find the hardware design guide useful as it goes over these types of things:
Note that VCAP1 and VCAP2 each need a 2.2uF to ground. Will likely work okay with just one, but it's easy enough to follow the recommendations if you're building a new board.
Pullup on NRST is not needed, just a 0.1uF to GND. Won't hurt anything.