STM32H7 with active D-Cache and sdMMC with DMA

[Brussl]

I try to start working sdMMC with DMA. When D-Cache is not active work well. But when turn it on stop work. Probably need to create MPU region , but where is located used RAM from sdMMC. And if need, how to change .ld file?

[mƎALLEm]

Hello,

You need to apply the cache maintenance when you enable the D-cache when using another master DMA/SDMMC/  CM4 (in dual core). You can disable the cache for the shared memory between the CM7 and the other master using the MPU (MPU policy: Device) but that decreases the performance.

Please refer to the application note AN4839 "Level 1 cache on STM32F7 Series and STM32H7 Series" / especially the section 3.2 Example for cache maintenance and data coherency.

The different available solutions:

Hope that answers your question.

[Brussl]

OK. And what is the region of RAM used by sdMMC ? The MCU is one core ,. just need to stop caching in this region. As I see sdMMC used MDMA. But where is allocated RAM? 

[mƎALLEm]

Please read the documentation especially the user manual of the product. From RM0433:

The memories accessible by SDMMC1 and SDMMC2:

The RAM used by the SDMMC depends on the user configuration in his application.

[DmitryR · Accepted solution]

Hi @Brussl ,

RAM for sdMMC is the buffer you supply to subsequent functions. But using separate non-cacheable MPU region for their placement is not a good idea as it forces you to use static buffers at fixed address or dynamically reconfigure MPU. Both are not a good programming practices.

Actually buffers for reading and writing sdMMC may reside in any region reachable by the DMA of the sdMMC controller. When you read, just before using the buffer being read you should invalidate the cache for the memory region used by the buffer calling SCB_InvalidateDCache_by_Addr. When you write, you should call SCB_CleanDCache_by_Addr just before triggering the write.

With best regards,

Dmitry

[Brussl]

Ok DmitryR , and what is address and size that can invalidate ?

[DmitryR]

Hi @Brussl ,

It is the address and size of the buffer that you supply to the subsequent HAL functions, HAL_SD_ReadBlocks and HAL_SD_WriteBlocks. If you use some file system then they are the buffers that you supply to the subsequent file system functions. 

Regards,

Dmitry

[Tesla DeLorean]

You provide the buffering memory, so a buffer you create/own, or one propagated down from the user's file system code. You might want to check the addresses passed, and use a staging buffer, or decompose the transfer into smaller pieces which fit within your own staging buffer.

For the file system, depending on the transfer size, file alignment, sector spanning, etc the file system may provide it's own buffer, or you might be using a section of the user supplied buffer, ie from f_read()

DMA buffers should be 32-bit aligned.

The Dcache functions anticipate 32-byte alignment, and length, otherwise there is the potential for collateral damage/impact. Invalidate Dcache throws away content, so stuff potentially in Write Buffer(s), or being stacked, if using buffers in auto/local variables.