I am trying to understand how the ECC IRQs work. I have configure the RAMECC1 AXI SRAM, RAMECC2 SRAM1, 2 and 3, and RAMECC3 SRAM 4 monitor CR registers to generate interrupts on double bit errors. I have configured the IER so that Global interrupts are NOT generated.
I've initialised all but the last 1K of the each of the SRAMs, so that my application can read from these addresses, when requested, to generate a ECC ISR and therefor test the handling of the error.
However, I have noticed that the ISR is raised to both cores (CM7 and CM4) regardless of which core performed the memory read triggering the ECC error.
Is there a way to configure the ECC or Interrupts so that only the core performing the read gets interrupted?
