STM32H7 DMA: what are the destinations for dmamux1_evt[3..15] signals?

[Evgeniy Bobkov]

There is the Figure 80 "DMAMUX block diagram" in the STM32F743 Reference Manual (RM0433), which shows that there is 'm' number of dmamux_evt signals, where 'm' is 16 for DMAMUX1 (the number of DMAMUX1_CmCR channels).

The Manual only describes the destinations for dmamux1_evt[0..2] signals in the Table 117 "DMAMUX1: assignment of trigger inputs to resources" and Table 118 "DMAMUX1: assignment of synchronization inputs to resources", while it does not describe the destinations of dmamux1_evt[3..15] signals.

My question is: what are the destinations of dmamux1_evt[3..15] signals, where do they come to as inputs after leaving the DMAMUX1 block?

[Tesla DeLorean]

I think this is an IP macro cell, indications are only four events are wired to anything, and dead nodes have been eliminated.

[Evgeniy Bobkov]

Clive, just to clarify, do I correctly understand that evt[3..15] are connected to virtually nowhere? And by "four" you mean three evt[0..2]?

[Tesla DeLorean]

Actually I think it's eight inputs, didn't notice there were two columns