Not sure why my previous post was marked as spam:
Hello,
I'm trying to do something relatively simple but can't figure out the issue. It might also be possible that there is no issue and my expectations are wrong about timer synchronization.
I am using TIM1 as a master with trigger out event configured when the timer is enabled. Enabling timer1 should start TIM2 and TIM15 (both configured as slave with appropriate ITR0 triggers).
Just for debugging and simplicity all the timers are using the same prescaler and the same period (ARR register value is the same).
The timer do start when I enable timer1 as expected. But they are not synchronized.
Below are registers dump for tim1, tim2 and tim15 just before setting TIM1.CR1 enable bit. Once I set the enable bit I get the logic analyzer capture shown.
I mean it works in the sense that enabling TIM1 triggers TIM2 and TIM15 but why aren't they synchronized?
Here is the code. I am using HAL for simplicity but I did try direct register manipulation but outcome was exactly the same.
HAL_TIM_OC_Start_IT(&htim2,TIM_CHANNEL_3);
HAL_TIM_OC_Start_IT(&htim15,TIM_CHANNEL_2);
HAL_TIM_OC_Start_IT(&htim1,TIM_CHANNEL_1);
On the surface it appears to work but when I zoom in on the first rising edge :
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Still looks like it could be a rise time issue. TIM1 is fastest, and overshoots, so the edge happens there first. TIM2 by comparison is much slower, no overshoot. Analog capture speed isn't quite high enough to say with certainty.
They all start going high at about the same time. Just takes longer for some channels to hit the threshold.
Could be a scope channel issue, but unlikely. Swap channels to eliminate that possibility.
There can be subtle timing differences between master/slave and timers not on the same bus. Changing the starting CNT value can shift things with the resolution of one timer tick.
@TDK Thanks for the great suggestion of doing an analog capture. I somehow got too deep in the digital troubleshooting and forgot to look for potential analog problems.
Here is the analog capture. As you can see it has the same kind of behavior. I did make sure that the alternate functions pins for output compare where set to very high frequency. Didn't make any difference probably because those three pins I use for Timer output compare are not connected to anything except the high input impedance of the logic analyzer.
That however gave me an idea and looking at the chip pinout I realized that TIM5 output compare channel 2 is also accessible on the same pin I used for TIM15. This allowed me to do another test but with Tim2 and Tim5 configured as slave this time with exactly the same probing setup.
Interestingly Tim2 and Tim5 are way more in sync as you can see below. Is it possible that since Tim2 and Tim15 are not on the same APB bus that is why I get this weird synchronization issue?Tim15 is also a timer with dead time and break support so maybe there is something to it?
That being said I'm still puzzled as you are as to why Tim15 output compare channel is going up before the timer 1 output compare channel.
I really need to use TIM15 or TIM12 because other timers are not available as an input trigger for the DMA operations I need. That made me look at using TIM12 and indeed it is also way more in synch. So everything leads to it being a problem with TIM15 but I am not sure why.
Still looks like it could be a rise time issue. TIM1 is fastest, and overshoots, so the edge happens there first. TIM2 by comparison is much slower, no overshoot. Analog capture speed isn't quite high enough to say with certainty.
They all start going high at about the same time. Just takes longer for some channels to hit the threshold.
Could be a scope channel issue, but unlikely. Swap channels to eliminate that possibility.
There can be subtle timing differences between master/slave and timers not on the same bus. Changing the starting CNT value can shift things with the resolution of one timer tick.
I see what you mean on my latest experiments but on the example with TIM1, TIM2 and TIM15 which was my original question even in analog mode you can see that TIM15 seem to really start before TIM1 which is still odd
I'll try with a scope later today and report back to see if the logic analyzer slower sampling rate could be the issue
