I would like to know the process size used in the STM32G4xx. I understand the 'F4, L4 and G0 are 90 nm and the 'H7 is 40nm. My interest stems from an application in a high RF environment, where larger process size would seem to be more robust(?)
As always, thank you for your responses!
> larger process size would seem to be more robust
IMO such assertion is moot.
There are surely dozens of parameters which influence RF/noise/whatever susceptibility more than the minimum feature size alone. Sure, with decreasing feature size the voltages generally tend to decrease too, so would everything else be the same you'd have relatively Moore Noyce, but IMO "everything else be the same" is far, far from being the case.
I'd say, the package alone has in practice more impact than the process node. I did not investigate this, though, so my opinion is just as good.
Silicon process technology: 90nm eFlash Generic TSMC
Other Device(s) using same process: STM32L4x product family
Thank you for the prompt answer! I agree with your general comments as well, and was hoping the answer was 90nm (and not 40nm). Device will be within an antenna mast, so technically resembling a Farady cage, but trying to be cautious all around none the less (> 1KW).