I am using an event as an external clock input into the Advanced Control Timer (TIM1) on a STM32G0x series MCU.
For my application it will be nice to low pass filter the signal using the internal "Filter Downcounter" in the chip.
I don't understand the internal digital logic of the filter, nor can I find detail on how this Digital Filter works (Flip-Flops, ect...), but here is my theory and hopefully someone can please share more detail or correct me.
This is the diagram in the datasheet.
Inputs into filter: N(amount of samples) , fdts(counter frequency), ETRP(event signal)
I assume, the filter is a type of counter. If there is N consecutive events in the logic signal for 1/f(dts) time. The output logic signal of the filter contains one pulse.
After 1/f(dts) time, the filter resets the internal counter. Or if there is no event triggered in the signal, when an event was expected. Hence, it has to be, consecutive positive event triggers.
Now, f(dts) is related to the input clock frequency in the Datasheet. The sampling period of this t(dts), can be set to the following settings in the datasheet:
Solved! Go to Solution.