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STM32G0B1 LSECSS error

Sunwaz
Associate III

‎2025-01-20 12:46 AM

Hello, ST expert

I'm using the STM32G0B1RCT6 and have enabled the LSECSSON. I've discovered a rather incredible phenomenon. I'm using a 3.3V battery for VBAT. When I disconnect the VDD of the MCU, it abnormally triggers the LSECSS fault. As a result, after disconnecting the VDD of the MCU, the system uses the LSI as the RTC clock. However, the LSI cannot operate in the VBAT voltage domain.

 

Below is my log：

« 
hello world!
 
DR:[0x2101] TR:[0x00] BDCR:[0x00]
DR:[0x2101] TR:[0x00] BDCR:[0x00]
DR:[0x2101] TR:[0x00] BDCR:[0x00]
 
not init backup domain! BDCR:[0x00]
Init LSE BDCR:[0x00]
Set RTC Source to LSE BDCR:[0x03]
Enable LSE CSS BDCR:[0x103]
Enable RTC BDCR:[0x123]
Backup register BDCR:[0x8123]
 0: 0: 0 1- 1-2000RCC->BDCR is [0x8123]
 0: 0: 1 1- 1-2000RCC->BDCR is [0x8123]
 0: 0: 2 1- 1-2000RCC->BDCR is [0x8123]
 0: 0: 3 1- 1-2000RCC->BDCR is [0x8123]
<<<Vdd is lost>>>
hello world!
 
DR:[0x2101] TR:[0x00] BDCR:[0x8200]
DR:[0x2101] TR:[0x03] BDCR:[0x8200]
DR:[0x2101] TR:[0x03] BDCR:[0x8200]
 
LSE is not enable! BDCR:[0x8200]
LSI is not Enable! BDCR:[0x8200]
Init LSI! BDCR:[0x8200]
Enable RTC BDCR:[0x8200]
Backup register BDCR:[0x8200]
 0: 0: 3 1- 1-2000RCC->BDCR is [0x8200]
 0: 0: 4 1- 1-2000RCC->BDCR is [0x8200]
 0: 0: 4 1- 1-2000RCC->BDCR is [0x8200]

 

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3 REPLIES 3
Sunwaz
Associate III

‎2025-01-20 01:27 AM

Sunwaz_0-1737365164644.png

Is the LSECSS detected after the power supply of the backup domain is switched from VDD to VBAT?

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Sunwaz
Associate III

‎2025-01-20 05:35 PM

Sunwaz_0-1737423301820.png

It's not certain whether this is caused by this defect, but it is indeed mentioned in the errata manual.

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Sunwaz
Associate III

‎2025-01-20 06:39 PM

One solution that comes to my mind is to enable the PVD and disable the LSE CSS function within the PVD. Then this problem can be avoided.

My log：

 
hello world!
PVD set!
Set PVD High Level is 2.2V PWR->CR2:0x102
Set PVD Low Level is 2.9V PWR->CR2:0x10A
Set PVD interrupt XTI->IMR1:0xFFE90000
Set PVD triger XTI->FTSR1:0x10000
Enable PVD PWR->CR2:0x10B
 
DR:[0x2101] TR:[0x00] BDCR:[0x8103]
DR:[0x2101] TR:[0x116] BDCR:[0x8103]
DR:[0x2101] TR:[0x116] BDCR:[0x8103]
 
Set RTC Source to LSE! BDCR:[0x8103]
Enable LSE CSS BDCR:[0x8103]
Enable RTC BDCR:[0x8123]
Backup register BDCR:[0x8123]
 0: 1:16 1- 1-2000RCC->BDCR is [0x8123]
 0: 1:42 1- 1-2000RCC->BDCR is [0x8123]
PVD
PVD
 
hello world!
PVD set!
Set PVD High Level is 2.2V PWR->CR2:0x102
Set PVD Low Level is 2.9V PWR->CR2:0x10A
Set PVD interrupt XTI->IMR1:0xFFE90000
Set PVD triger XTI->FTSR1:0x10000
Enable PVD PWR->CR2:0x10B
 
DR:[0x2101] TR:[0x00] BDCR:[0x8103]
DR:[0x2101] TR:[0x145] BDCR:[0x8103]
DR:[0x2101] TR:[0x145] BDCR:[0x8103]
 
Set RTC Source to LSE! BDCR:[0x8103]
Enable LSE CSS BDCR:[0x8103]
Enable RTC BDCR:[0x8123]
Backup register BDCR:[0x8123]
 0: 1:45 1- 1-2000RCC->BDCR is [0x8123]
 0: 1:46 1- 1-2000RCC->BDCR is [0x8123]
 0: 1:47 1- 1-2000RCC->BDCR is [0x8123]
 0: 1:48 1- 1-2000RCC->BDCR is [0x8123]
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