stm32f746bg and MX30LF2G NAND Flash

[nafikovr]

Posted on June 28, 2016 at 14:55

FMC Configured as

hnand1.Instance = FMC_NAND_DEVICE;
/* hnand1.Init */
hnand1.Init.NandBank = FMC_NAND_BANK3;
hnand1.Init.Waitfeature = FMC_NAND_WAIT_FEATURE_ENABLE;
hnand1.Init.MemoryDataWidth = FMC_NAND_MEM_BUS_WIDTH_8;
hnand1.Init.EccComputation = FMC_NAND_ECC_DISABLE;
hnand1.Init.ECCPageSize = FMC_NAND_ECC_PAGE_SIZE_2048BYTE;
hnand1.Init.TCLRSetupTime = 2;
hnand1.Init.TARSetupTime = 2;
/* hnand1.Info */
hnand1.Info.PageSize = 2048;
hnand1.Info.SpareAreaSize = 64;
hnand1.Info.BlockSize = 64;
hnand1.Info.BlockNbr = 2048;
hnand1.Info.ZoneSize = 2048;
/* ComSpaceTiming */
ComSpaceTiming.SetupTime = 0x5;
ComSpaceTiming.WaitSetupTime = 0x3;
ComSpaceTiming.HoldSetupTime = 0x2;
ComSpaceTiming.HiZSetupTime = 0x5;
/* AttSpaceTiming */
AttSpaceTiming.SetupTime = 0x5;
AttSpaceTiming.WaitSetupTime = 0x3;
AttSpaceTiming.HoldSetupTime = 0x2;
AttSpaceTiming.HiZSetupTime = 0x5;
HAL_NAND_Init(&hnand1, &ComSpaceTiming, &AttSpaceTiming);

after firsy calling HAL_NAND_Read_ID() MCU generates 32 NRE strobes (why 32 times if readed only 32 bits?) and return valid data. if i call this function one more time no NRE strobes has been generated, but function return valid data. also i try to read ONFI signature after reading ID and no NRE strobes and reading returns last readed data (ID). somebody can help with this problem?

[troy1818]

Posted on June 28, 2016 at 15:49

Hi,

It is very important that the configuration is correct. From the spec: 2G-bit/4G-bit SLC NAND Flash- Bus: x8- Page size: (2048+112) byte,- Block size: (128K+7K) byte,- Plane size:1024-block/plane x 2 for 2GbUser Redundancy- 112-byte attached to each pageIf you are unsure about timing then just crank up the values somewhat for the timing and see if anything changes.

[waclawek.jan]

Posted on June 28, 2016 at 20:02

You're probably hit by a cache-gotcha. While [DEAD LINK /public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/STM32F7%20NOR%20memory%20with%20FMC&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=511]this thread deals with NOR FLASH which is at Bank1, the Bank3 area is AFAIK cached by default too.

JW