STM32F745 SPI compatibility with exteranl ADC LTC1403A and AD7274

[lopezcontreras]

Dear All,

I am working on a new design with STM32F745 and an external ADC of 2-3 Msps range.

I have two ADCs candidates: LTC1403A (14 bits/2.8Msps/SPI) and AD7274 (12bits/3Msps/SPI). Please find attached datasheet for your reference.

The maximun SPI frequency of STM32F745 is 50Mbit/s, for LTC1403A is 50.4 and for AD7274 is 48.

I have a couple of questions:

(1) LTC1430A SPI CLK is 50.4 MHZ, I could run in on 50Mhz, but however (see diagram LTC1430A Timing Diagram on pag. 9 of datasheet) It needs 18 SCK cycles. So I understand that I can not use it because on STM32F754 only accepts 8 or 16 bits protocol. Am I correct? Is there anyway to configure 18 SCK cycles on STM32F745 to read from LTC1430A?

(2) AD7274 is 12bits but as can be seen on figure 7, pag 8 (Timing example 2) it only needs 16 SCK so it is compatible with STM32F745 micro. Dou you agree? Is there any other thing to worry about it?

Thanks in advance for you support.

Regards,

Joaquín.

[TDK]

> Is there anyway to configure 18 SCK cycles on STM32F745 to read from LTC1430A?

The SPI frame size can be set in SPIx_CR2_DS. 18 bits is not an options, but two 9-bit transfers would achieve the same thing.

> AD7274

This one would work as well.

> Is there any other thing to worry about it?

You're still going to have difficulty transferring at this speed since you need to control the CS line as well. It's possible to do this, but it is not straightforward. Trying to send ~50 Mbps over the DMA bus may also be problematic.

[lopezcontreras]

Hi TDK,

Thank you very much for your help.

Regardign your phrase "You're still going to have difficulty transferring..." I am not sure if I understand. For CS line, I was thinking to connect it on NSS signal as output when using STM32CubeIDE to configure the SPI as a Receive Only Master. Do you see problem on this? Could you be more specific?

Thanks in advance,

Joaquin.

[TDK]

The NSS pin does not toggle for each frame. It is low when the peripheral is enabled. For this reason, typically it is controlled by software as a GPIO pin, which is going to pose problems at such a high transaction rate.

[lopezcontreras]

Hi TDK,

Thank you very much for your support.

On datasheet of STM32F745, fig. 46, and fig 47 (pag 157 & 158) for slave configuration show that NSS input toggle to low level for a frame. For master configuration, fig. 48, it seems that not toggle. However, I have tested these signals on a NUCLEO-F439 board and it seems that NSS toggle. Please find attached pictures that I have taken in a 60Mhz oscilloscope. They corresponde to the NSS signal and SCLK (f 42MHz). One is in a "full master" configuration and the other one as "only receive Master". In both cases NSS is gneerated and hold low for the full frame.

So, are you sure that NSS is not toggling? What am I missing?

Thanks in advance,

Joaquin.

[lopezcontreras]

And the other picture

[TDK]

In regular mode, NSS doesn't toggle. In TI mode, a pulse on NSS is output one clock before the MSB. TI mode is not commonly used, but it may work for you here. You would need to increase the frame size by 1 bit and ignore the data coming in when NSS is high. See "TI mode" in the reference manual.

 

I'm going to assume the bad rise/fall time in your signals is due to the scope bandwidth/issues and isn't present on your actual board.

[lopezcontreras]

Hi TDK,

Yes, the first thing, bad signals waveforms is due to the my oscilloscope of only 60Mhz.

I think NSS signal also toggle with Motorola mode...see Fig.371 of the Reference Manual RM0385.

So, in my opinion, STM32F745 SPI port is fully compatible with AD7274, without major difficulties.

Thanks again for you support.

[TDK]

Hmm. Maybe that’s the “NSS Pulse�? setting or something. Apologies for the misinformation, but glad it’ll work out. I’ll have to check that out again at some point.