Posted on February 26, 2018 at 14:19According to the table 86 in STM32F777xx datasheet, the max SPI clock in master mode for SPI1,4,5,6 is 27 MHz (at 1.7 Vdd). However, if I setup the STM32F777 in STM32cubeMX for 1.7 Vdd operation, and use the max HCLK at 180 MHz (table 19), the resulting clock for SPI1 is 45 Mbits/s. Are there any other other limitiations for 1.7 Vdd operation or is there a typo in the datasheet?
The max SPI clock of 27 MHz listed in the table 86 in the STM32F777x datasheet seems to be derived from 216 MHz HCLK, which, according to the table 19 should not be feasible, as the max listed HCLK for 1.7 Vdd is 180 MHz.
