2015-09-29 12:56 AM
What is the correct way to set the SRAM1 & SRAM2 as NON-CACHEABLE? I am using STM32F746 and the Discovery board.
2015-09-29 01:10 AM
Using MPU?
https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy.st.com%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fSTM32F7%20NOR%20memory%20with%20FMC&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&c... JW2015-09-29 02:02 AM
Hi dimitrov.valentin,
You can modify memory region altering MPU attributes.I'd highly recommend you to have a look to the MPU project under STM32Cube F7 package:STM32Cube_FW_F7_V1.1.0\Projects\STM32756G_EVAL\Examples\Cortex\CORTEXM_MPU, it can be very useful.-Syrine-2015-09-29 04:04 AM
Here's my code for the MPU initialization
static void MPU_Config(void){
MPU_Region_InitTypeDef MPU_InitStruct;
/* Disable the MPU */
HAL_MPU_Disable();
/* Configure the MPU attributes as WT for SRAM */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x20010000;
MPU_InitStruct.Size = MPU_REGION_SIZE_256KB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* Enable the MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
} I have a timer triggering ADC conversions every 4 seconds and DMA2 is collecting 12 samples in adc_buf. When adc_buf is placed for example on address 0x20040000 (0x20010000 + 192K) or higher the data is cached and i only see the default values with which adc_buf was initialized. If adc_buf is placed on addresses between 0x2001000 and 0x2003fc00 it seems to work :) i can see the new samples values every 4 seconds. When i disable the data cache the problem disappear.
2015-09-30 01:17 AM
It appears that there is an error in the ST F7 examples. According to ARM
v7-M Architecture Reference Manual:''The base address, size and attributes of a region are all configurable, with the general rule that all regions are
naturally aligned. This can be stated as:
RegionBaseAddress[(N-1):0] = 0, where N is log2(SizeofRegion_in_bytes)'' which is not correct for base address 0x20010000 and region size of 256KB. So in this case 4 regions of 64KB must be initialized in the MPU with base addresses: 0x20010000 0x20020000 0x20030000 0x20040000