2018-09-11 05:30 AM
I am reviewing the stm32f4xx_hal_spi.c to setup the SPI interface for Master mode DMA receive-only use. I notice the table showing that in this mode the maximum SPI frequency is Fpclk/64. I haven't bench tested this yet but was curious why this is so much slower then the same configuration but in 2Lines full-duplex operation.
2018-09-11 07:01 AM
SPI in Rx-only mode starts to transmit clocks autonomously as soon as it's enabled and it won't stop until disabled again. The lower speed thus may be because of that software succeeds in disabling SPI just "inside" the last frame (byte) to be received.
I don't Cube.
JW
2018-09-11 07:31 AM
Thanks for that analysis; I will explore that idea in the code.
2018-09-11 01:43 PM
Because of this limitation, I ended up setting up the DMA to be one byte less than the transfer. Then, I used the DMA transfer completion interrupt to disable the SPI peripheral. Any transfers in progress aren't stopped. I busy wait poll for the transfer to complete and then negate the chip select.
The interrupt priorities and system timing is designed to support this.
If I had to do it over again, I would never use two wire SPI mode because of the poor SPI peripheral implementation. It wouldn't have been very hard for the design to support the RX length and then it would stop after that. Oh, well.
I cannot remember but the USART may be better for this but don't quote me on it.
2018-09-14 07:16 AM
Thanks for sharing that Nickname3397; I will investigate that as a possible solution for my application.