Posted on July 28, 2015 at 20:25Ok, but the 6800/8080 busing scheme relates to these 1970-1980's era parts for which prolific amount numbers of books and teaching texts, dealing with microprocessor interfacing, cover this area.
The F4 FSMC provides for an external bus, with chip selects, using wide data and address buses. Beyond the data bus width the FSMC provide a means of configuring the timing and sequencing of signals on the bus, providing significant opportunity to interface to all manner of devices, ie NOR, NANDFLASH, SRAM, FGPA, LCD, etc.
The reference manuals discuss the timing, and provide diagrams, the prerequisite of course is that you have sufficient experience and grounding to be able to use that data. The Reference Manuals are not targeted as tutorial material, but have an expectation that you're reasonably practiced in the art. There's at least 30 years of material you can refer back to, to give you whatever depth of understanding you need.
To gain some experience I'd suggest looking at how other 320x240 controllered displays are attached to STM32 parts, how the external buses are configured, and how the software accesses the registers and frame buffers in these devices. There's more commonality in how this is done than there are differences.
You'll need to review the LCD datasheets, and decompose the descriptions into timing and sequencing to for fill those requirements.
