stm32f429 rcc pllcfgr pllsrc bit will not set

[JKell.1]

I am trying to set RCC->PLLCFGR |= PLLSRC after setting RCC->CR |= HSEON and waiting for HSERDY to be presented.

I have tried this while with and without RCC->CR PLLON set.

The device will run fine from either HSI or HSE, and I verified the speed is the same (16MHz) both ways.

I can even get the PLL to start and run as expected using HSI. The problem is that my application's timing accuracy requirements are not met by HSI. I really need the 50ppm provided by the crystal.

Even using Keil tools' SystemViewer for RCC to flip this bit it immediately clears it again.

Any idea why the PLLSRC bit keeps immediately clearing itself?

[waclawek.jan]

> I am trying to set RCC->PLLCFGR |= PLLSRC

How *exactly*?

JW

[turboscrew]

"The device will run fine from either HSI or HSE, and I verified the speed is the same (16MHz) both ways."

You don't try to feed PLL from the HSE while HSE is feeding the core?

[berendi]

It does not happen at me, so what are you exactly doing?

int main(void) {
	RCC->CR |= RCC_CR_HSEON;
	while(!(RCC->CR & RCC_CR_HSERDY))
		;
	RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC;
	int i;
	for(i = 0; i < 100000; i++)
		__NOP();
	if(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)
		while(1)
			__NOP(); // good
	else
		while(1)
			__NOP(); // bad
}