STM32F429: GPIO logic level during power on

shiwei luan · ‎2018-03-26

Posted on March 27, 2018 at 03:10

What is the logic level of GPIO pins of STM32F429 during powering on?

I am using several GPIO pins as enable pins to enable downstream devices. These GPIOs must be 'LOW' during power on until the firmware actively enables them.

I tried to find information from datasheet, but this information is not specified. My question is: when STM32F429 is being powered on and before the firmware takes care of GPIO configurations, what is the status of GPIO, HIGH, LOW or HIGH Z?

Thank you.

waclawek.jan · ‎2018-03-27

Posted on March 27, 2018 at 09:46

Unless it's one of the JTAG/SWI pins, and unless you enable bootloader, they are floating - see RM0090 rev.15, 8.3.1 General-purpose I/O (GPIO).

Use an external pulldown if you need a defined logic level during powerup.

JW