Hi guys,
I'm using an stm32f427 interfaced with an external SDRAM by mean of FMC controller.
The controller is configured with SDRAM clock period = 2 x HCLK periods and to support burst read (RBURST bit = 1).
It's not clear to me how to set the RPIPE parameter since i haven't understood its actual purpose even if I have read the description "these bits define the delay, in HCLK clock cycles, for reading data after CAS latency".
Is this a delay needed by AHB bus to complete data transfer from SDRAM or is needed by SDRAM memory itself?
Is it just used to add an extra-data in controller cacheable FIFO (according to formula "CAS latency + 1 + (RPIPE delay) / 2)" ?
Has this parameter an impact on memory R/W cycle?
Up to now I have set it to one HCLK clock cycle delay (local rule of thumb : ).
I suspect that this setting is not meaningful and I don't know if it could affect read/write of data.
Here are some reference in case they can be of help
* STM32F427II @HCLK = 180MHz
* SDRAM @SDCLK = 90MHz, CAS latency = 3 (dev data-sheet http://www.issi.com/WW/pdf/42-45S81600F-16800F.pdf)
Thanks in advance for your help,
Stefano
