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STM32F407 with LAN8742A custom board init issue

VivekBorse
Associate

Hi 
I have created Ethernet custom board using STM32F407 + LAN8742A attached is my schematic design based on Nucleo board for STM32F429ZI.
on my custom board MX_LWIP_Init is getting error in HAL_ETH_Init in following section.

 

 

  /* Wait for software reset */
  while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U)
  {
    if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
    {
      /* Set Error Code */
      heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
      /* Set State as Error */
      heth->gState = HAL_ETH_STATE_ERROR;
      /* Return Error */
      return HAL_ERROR;
    }
  }

 

 

 For above issue I checked the clock freq at LAN8742A input is correct 25MHz.

I also followed the issues mentioned in this post https://community.st.com/t5/stm32-mcus-embedded-software/how-to-make-ethernet-and-lwip-working-on-stm32/m-p/261456
still facing the same issue.

Also check my PCB file to verify the placement and routing and suggest the changes if there are any files attached. 

the application I configured is working on nucleo board but the same configurations not working on custom hardware. attached the application used for testing
Hi @Piranha, @Tesla DeLorean  Please help me resolve this issue this is my 3rd iterations on hardware but facing the same issue in all. this time I matched everything with nucleo board BOM.

3 REPLIES 3

Perhaps clocking / sequencing issue on the STM32F4 side

What's the external clock on the STM32? Is HSE_VALUE correct?

Shouldn't single VCAP be 4u7 ? Not sure issue here.

If you have a working board, check register setting on that vs yours. Look at pins electrically too.

Check DMA settings, what errors/status that's reporting. Confirm timeout duration.

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STea
ST Employee

Hello @VivekBorse ,

this seems to be a clock issue in MCU side so check the following:

Check presence of the clock using oscilloscope and make sure is precise, check also if the MII/RMII switch is properly set in SYSCFG_PMC.MII_RMII_SEL

- check if all three ETHMACxxEN bits in RCC_AHB1ENR are set 

also, after a quick check of your design I find that it is not compliant with the schematic of the Nucleo F429 which embedded the same PHY.

the RXFER/PHYAD0 pin has 33-ohm resistor and in our schematic, we have a 10K resistor:

STea_0-1715627262355.png

Nucleo schematic 

STea_1-1715627308909.png

check also if the Capacitor values associated to your crystal oscillator is compliant because they can cause the PHY to not initialize properly hence not being able to de-assert the software reset bit.
also checked your software everything seems to be set properly and the issue is mostly in the design of the PCB.

BR

 

In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

HI @STea and @Tesla DeLorean,

thank you for quick responses 
1. I checked the SYSCFG_PMC.MII_RMII_SEL in debugging mode it is getting set properly. 

2. Controller External clk is 8MHz.
3. Tried checking DMA setting but controller goes in Error_handler after finishing HAL_ETH_Init() function

2. checked  ETHMACxxEN bits in RCC_AHB1ENR are set or not 
Before calling HAL_ETH_Init() 

WhatsApp Image 2024-05-14 at 6.03.17 PM.jpeg

 after calling HAL_ETH_Init()

WhatsApp Image 2024-05-14 at 6.03.18 PM.jpeg

 Changed the Resistor value for RXFER/PHYAD0 pin to 10K but issue is still same. on nucleo board after successful init I can observer 50MHz clock on Refclk0 pin but in case of custom board is not observed.

WhatsApp Image 2024-05-14 at 5.56.11 PM.jpeg

Following is the Clock signal observed for LAN chips on custom board with same of capacitor  value (30pf) similar to nucleo board.

WhatsApp Image 2024-05-14 at 5.58.32 PM.jpeg

with similar part number for oscillator for LAN as nucleo board following is observed on nucleo board 

WhatsApp Image 2024-05-14 at 5.59.30 PM.jpeg

 I request you to review the layout also to check weather the problem is in board or not so that I can resolve this issue as soon as possible.