STM32F407 VDDA-VREF+ difference

waclawek.jan · ‎2025-06-09

In the STM32F407 DS, ADC characteristics table has the following footnotes:

IMO 2. follows from 3. (which is a more stringent requirement); thus 2. is redundant and confusing.

JW

mƎALLEm · ‎2025-06-17

Hello,

Note 2, is related to the power-up phase while note 3 is related to the functional mode when the ADC is running.

So note 2 will be updated to mention that difference.

The proposed change:

2. When VDDA and VREF+ are supplied by independent voltage sources, during power-up phase, it is recommended to maintain the difference between VDDA and VREF+ below 1.8V.

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View solution in original post

mƎALLEm · ‎2025-06-09

Hello,

This will be escalated internally for analysis and fix. Internal ticket number: 211812.

Thank you.

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mƎALLEm · ‎2025-06-17

Hello,

Note 2, is related to the power-up phase while note 3 is related to the functional mode when the ADC is running.

So note 2 will be updated to mention that difference.

The proposed change:

2. When VDDA and VREF+ are supplied by independent voltage sources, during power-up phase, it is recommended to maintain the difference between VDDA and VREF+ below 1.8V.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

waclawek.jan · ‎2025-06-17

Thanks for the clarification.

JW