STM32F401 as I2C Slave Mode? Speed?

[LGrüb.1]

Hello Forum,

I want to use a Nucleo 64 STM32F401 Board to test I2C connection with an unknown master (reverse engineering).

The Bus consits of 1 Master (unknown Controller) an 1 Slave (My STM32F40). The Master sends out a Read Request at Addr. 5 and the Slave should respond with 3 Bytes. I've connected the I2C Bus to PB6/PB7 of the Nucleo Board. 

On Softwareside I Initialized with bare metal Code, see attachment.

I my setup a I2C Master sends out a Adress byte with read request to address 5, but my Controller doesn't do a thing at all. I would expect at least an ACK Bit, but nothing can be monitored.

From the Signal capture the bus looks fine for me, but in which mode do I need to configure the stm32 slave? Is this standard mode or fast mode. Is the clock speed of any concern in this case (slave)? How to config the CCR and TRISE register in this case.

The Port seems to be configured correct, the IDR of GPIOB detects a "1" on PB6/PB7.

In my example I've also enabled interrupts, but no interrupt occurs, nor also a main loop check of the RXNE register shows any activity. Also swapping Pins to PB8/PB9 didn't change anything. Setup is attached.

Does someone has any hint to bring up the slave mode or to check even liveness of the I2C of the STM32 Controller?

regards, Lorenz

[TDK]

The clock in the picture is about 200 kHz, which is not a standard speed, but meets the criterion for fast mode (up to 400 kHz).

The signal is trying to talk to slave 0xB << 1. Your code sets up slave 0x5 << 1. These are not the same so the controller should not respond.

> // Slave-Adresse setzen (z.B. 0x50)
> I2C1->OAR1 = (0x05u << 1) | (1 << 14); // 7-Bit Adresse, Mode 0

Your comments looks like your'e trying to set the slave address to 0x50.

[LGrüb.1]

Hello TDK,

thank you for Answering and notice my mistake

my intended Adress is 0x05u

also changing the OAR Register to

    // Slave-Adresse set (z.B. 0x05)
    I2C1->OAR1 = (0x0Bu << 1) | (1 << 14); // 7-Bit Adresse, Mode 0

didn't changes anything, my main concern is that something could fail because of the odd I2C Speed. What is actually the difference between Standard and Fast mode? ( I just set the I2C_CCR_FS-Bit to switch to fast mode).

Would running the I2C Bus also operate in Standard mode solve the inresponsiveness?

regards,

Lorenz

[TDK]

> my main concern is that something could fail because of the odd I2C Speed

Why do you have this concern? There is no reason for it.

This is not a bus speed issue.

[Ozone]

> I my setup a I2C Master sends out a Adress byte with read request to address 5, but my Controller doesn't do a thing at all. I would expect at least an ACK Bit, but nothing can be monitored.

That is an issue with your code, not the physical bus.

You would need to configure your MCU to accept this address. Check with the RM how the 7-bit address is interpreted, either to be shifted or OR-ed. This part is not handled consistent across device documentations.

[LGrüb.1]

Hello,

thank your for adivces,

currently I've swaped SDA/SCL Pins just for Testing, suddenly the I2C Error Interrupt with BUS Error Bit Active is fired, so my conclusion now is that the I2C Block doesn't see the SCL Signal at all, I think it is related either to termination or Voltage Level of the SCL Line. I'll try to investigate further in signal quality.

Also changing the Address to 0x05<<1 doesn't change anything, so I think the problem is on the electrical side.

thanks you

Regards,

Lorenz

[Ozone]

> ... didn't changes anything, my main concern is that something could fail because of the odd I2C Speed. What is actually the difference between Standard and Fast mode?

The bus logic of most I2C devices is basically a static design, i.e. independent of the clock - as long as you remain below the limit. You can even single-step through signal transitions, at least with bit-bang code.

The I2C standard is relatively old, and the "standard mode" only reflects device limitations of that time.

[Ozone]

> I think it is related either to termination or Voltage Level of the SCL Line.

I suppose you do have pull-up resistors, they are essential for I2C functionality.
And the internal pull-ups (about 40k) don't work, you need about 1...10k, I usually go with 2.2k.

> Also changing the Address to 0x05<<1 doesn't change anything, ...

Just a guess - shouln't the slave address be '2' in this case ?
(I.e. 2<<2+0=4 for WR, and 2<<2+1=5 for RD)

[LGrüb.1 · Accepted solution]

Hello Ozone,

thank you for yout thought,

I've lowered Pull ups to 2k2 and installied 33E Protection Resistor, the signal slopes are better now. What I've noticed is a thing in Initialization if I2C

when I try to set Acknowledge enable (like in my Init Funktion)

     I2C1->CR1 |= I2C_CR1_ACK;

it is ignored during Initalization when the I2C Block is in PE=0 modei, so moving Acknowledge enable together Enable Bit to

    /* Enable the selected I2C peripheral and set ACK Mode */
    I2C1->CR1 |= I2C_CR1_ACK | I2C_CR1_PE;

the I2C Block starts to operate.

I've misinterpreted the paragraph in the Reference Manual

Bit 10 ACK: Acknowledge enable
This bit is set and cleared by software and cleared by hardware when PE=0.

I thought this bit is cleared when entering "PE=0" and can be set anytime again during initialization.

thank you for you help,

Regards

Lorenz