2014-07-08 12:30 AM
Hi,
I’m trying to minimize control loop delays. Based on a certain analog value (adjustable threshold) a digital output is triggered. Reading ADC values is done by using DMA, digital outputs are driven without DMA.
Results measured by scoop: minimum delay ~300 μs, variation ~90 μs (min
300 μs,
max
390 μs
) Does anybody have some tips/tricks/best practices minimizing ADC-DO control loop delays?Thanks.
2014-07-08 01:26 AM
Hi
''I’m trying to minimize control loop delays. Based on a certain analog value (adjustable threshold) a digital output is triggered. Reading ADC values is done by using DMA, digital outputs are driven without DMA.
'' ''Does anybody have some tips/tricks/best practices minimizing ADC-DO control loop delays?
'' Not sure what you mean by 'ADC control loop' ?? Try looking at the 'Analogue Watchdog' feature of the ADC. It is basically 2 threshold values which can trigger an IRQ2014-07-08 02:21 AM
Why not using a discrete comparator, or a stm32f3 with integrated comparators ?
That would remove much software-induced delays from the loop. For better suggestions, you might perhaps reveal more details about your application.2014-07-08 04:22 AM
A singular ADC value, how frequently? Perhaps you could avoid DMA, or use an alternate ADCx unit, and use the EOC interrupt to read/process the threshold