Sorry, I have another question to ask everyone. I'm currently using the Nucleo F429ZI with SPI interface to receive 12-bit encoded data from another ADC. The Vdrive of that ADC can provide 3.3V or 5V for driving. However, the high level of the STM32F429ZIT6 is 3.3V. If I want the SPI high level to be 5V, what methods can I use to achieve this?
Originally, I was researching GPIO's Open Drain to use an external 5V to accomplish this, but in CubeIDE, the SPI is set to Push-Pull. So I would like to ask, when using STM32, how can I achieve a 5V high level if the SPI requires it?
Hello @Scarlet ,
It's possible to setup the configuration described and speaking about 5V tolerant pins only in input mode.
When the output mode is enabled, the GPIO is no more 5V tolerant.
It could work based on next principle for I2C. Taking into consideration that problematic could be difference between VDD and VDDx, which should never exceed 3.6 V:
Because this ADC can use a higher SPI frequency with a Vdrive of 5V, I want to try if it's possible to reduce processing time.
Or a 5v tolerant gate as level shifter at 3v3 VDD (VHC or UHC series have such ).
I will check the level shifter aspect. I plan to use the MAX14850AEE for voltage conversion, but this is not the optimal solution. However, I will further research this area. Thanks.
Only for inputs (here) can use a voltage divider, like 2k - 3k3 -gnd. So input at 3v3 max.
The voltage divider is like this?:
>The voltage divider is like this?: yes, but without the short to 5V . :)
But need lower impedance resistors, at 2k /3k3 it might work up to 10MHz - but never 50MHz.
+
as level shifter gates i use something like this :
SN74LVC1G86 (single XOR gate ; at mouser 20ct , 595-SN74LVC1G86DCKR )
so need one for every line :
At 50MHz this is the way to go ; LVC gate can switch in 1.3ns at 3v3 (50pF load), so perfect here.
