STM32F4 SPI high level 5V

[Scarlet]

Sorry, I have another question to ask everyone. I'm currently using the Nucleo F429ZI with SPI interface to receive 12-bit encoded data from another ADC. The Vdrive of that ADC can provide 3.3V or 5V for driving. However, the high level of the STM32F429ZIT6 is 3.3V. If I want the SPI high level to be 5V, what methods can I use to achieve this?

Originally, I was researching GPIO's Open Drain to use an external 5V to accomplish this, but in CubeIDE, the SPI is set to Push-Pull. So I would like to ask, when using STM32, how can I achieve a 5V high level if the SPI requires it?

[Scarlet]

OK, I know how the 74LVC1T45 operates now.

[Uwe Bonnes]

To get such a timing, try following approach. Set channel 1 to get low after t(quiet), channel 2 to get low after t(quite) + t(conv) + some margin.With ch2 getting low, start a DMA transfer to SPI TX. Make the period quiet+conv+ spi-readout + some margin. With timer update either read out SPI via interrupt  or send a signal via DMA to read SPI to memory. SPI version 3, as on U5, can generate NSS by itself, so only channel 1 is needed.

[David Littell]

How fast do you intend to run /CNVST?

[Scarlet]

@David Littell 

Are you asking how soon after completing SPI reception, how fast run the next CNVST?
Currently still in testing, theoretically aiming for as soon as possible.

[Scarlet]

@Uwe Bonnes 

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To get such a timing, try following approach. Set channel 1 to get low after t(quiet), channel 2 to get low after t(quite) + t(conv) + some margin.With ch2 getting low, start a DMA transfer to SPI TX. Make the period quiet+conv+ spi-readout + some margin. 

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I'm not entirely clear on this passage. channel 1、2 is ADC channel or another SPI register?

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With timer update either read out SPI via interrupt  or send a signal via DMA to read SPI to memory. SPI version 3, as on U5, can generate NSS by itself, so only channel 1 is needed.

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So, is it possible to enhance SPI efficiency through interrupts? I'll test it out and see.

 SPI version 3, as on U5, can generate NSS by itself, so only channel 1 is needed.

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I'll study this part further.

[Uwe Bonnes]

I meant a timer with two channel, where timing is done with output compare. And my last remark is not fully right, you still need the second channel to start the SPI transfer, but NSS could be produced by SPI-V3 and not the compare output of timer channel 2.

[Andrew Neil]

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@Scarlet wrote:

 is it possible to enhance SPI efficiency through interrupts? I'll test it out and see.

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Relative to what?

If you're using HAL, even the interrupt-based calls have a lot of room for optimisation...

In general, interrupt-driven will be better than polled, and DMA will be better still.

[Scarlet]

OK, Polling、Interrupt-driven I/O、DMA (Direct Memory Access)

Could possibly be optimized. I will research and test.

Thank you.

[Scarlet]

To achieve through timer & interruption. I got.

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but NSS could be produced by SPI-V3 and not the compare output of timer channel 2.

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But SPI-V3, I don't have much of a concept, and I haven't found relevant information either.

So I don't really clear the difference between NSS and using GPIO control.