STM32F4 - Master Receive

dibs · ‎2013-12-04

Posted on December 04, 2013 at 22:45

I am attempting to get an STM32F4 to receive data in Master mode. I am getting a problem where the RXNE interrupt is never tripped.

*Should this work, even if you have MISO tied to GND or 3.3V?

*Do I need to do anything with the NSS in the peripheral?

**Ignore the CS requirements of the slave for now.

#stm32f4 #spi

francescatodiego · ‎2013-12-06

Posted on December 06, 2013 at 15:41

The rules are:

When TXE set you can write to SPI_DR register (writing the SPI_DR clear TXE bit)

When RXNE set you can read from SPI_DR register (reading the SPI_DR clear RXNE bit)

You can check the bit status before read to/write from SPI peripheral or you can start an automatic control enabling interrupt/dma ....