STM32F373 SDADC injected conversion order

blechleitner · ‎2016-07-01

Posted on July 01, 2016 at 12:30

Dear ST Team,

along another issue I found in the F373 SDADC code, I saw a strange behaviour of the SDADC against the description in the F373 reference manual.

My software samples some sensors connected to multiple channes of one SDADC (Ch 7 & 8). Triggered by Timer 19 and the converting results are transferred into a memory buffer by means os the DMA. The memory buffer contains 32 bit wide items so I have the corresponding channel number for the specific conversion result available.

According to the reference manual D022448 Rev 4, chaper 13.5.4, the order shall be beginning from the highest number (ch 8) to the lowest number (ch 7). So I expect the first result belonging to channel 8 and the second one belonging to channel 7. but in reality, its just vice versa, I see the channel 7 as the first result in my buffer, channel 8 is the second one.

Is this just a bug in the reference manual or even a bug in the chip? I have checked the errata sheet as well, no indication to this behaviour.

Thanks in advance and best regards,

Bernhard Lechleitner

#f373-sdadc

mrechte · ‎2016-10-19

Posted on October 19, 2016 at 17:10

Hello. I am having the same problem. I configured 5 channels on SDADC1 (4, 5, 6, 7, 8) and data through DMA is returned in channel order not in reverse order.

So it means the SDADC makes conversion in channel ordre (0-8) not in reverse ordrer as states the doc several times (RM0313 rev5).