Hello,
we are using the HRTIM (Channel A) of the STM32F334 to trigger the ADC.
The data of the ADC is written to an uint16[3] array by using the DMA.
We disabled the IRQ for the specific DMA channel as the ADC value is used by the main program with lower sampling rate; thus, we minimized the interrupts.
As far as I know, that should be no problem as the DMA is configured in circular mode.
The trigger of the ADC has been selected to match with the capture compare unit of channel 1 of the HRTIM.
This configuration works most of the time, but when the CC is 90% of the timer period and we switch to e.g. 5%, the ordering of the channels in RAM are not consistent any more.
E.g. before the ordering was in0 in1 in2; after this change it is in1 in2 in0.
If the period is low enough, the maximum allowed ADC trigger frequency might be exceeded.
Can anybody confirm that this will cause the DMA not being in sync with the ADC any more?
Is this somewhere explained or is this a bug?
There is also an application note
https://www.st.com/content/ccc/resource/technical/document/application_note/ec/9c/b0/81/b5/12/4e/21/DM00108726.pdf/files/DM00108726.pdf/jcr:content/translations/en.DM00108726.pdf
which performs sliding ADC trigger event.
Best regards
Steffen
