STM32F303 I2C Clock Frequency

[philippe239955_stm1_stmicro_co]

Posted on October 12, 2016 at 15:57

Hello,

We are using I2C on a STM32F303 in master mode. We have computed the configuration of TIMINGR register using AN4235 (and CodeMX gives same results). We don't use clock stretching. We are facing an unexpected issue :

• The clock frequency measured on SCL is not the expected one. For 400kHz targeted, we measure roughly 382kHz.
• Moreover, we observe frequencies that differs significantly on different boards.

As a master, we would expect to measure on SCL a fixed frequency. After a lot of investigation, it seems that the effective load capacitance of the bus and its impact on the SCL rise time seems also to impact SCL frequency. In our application, the SCL rise time is not constant as the number of slaves can vary.

Is it possible that the SCL rise time is, by any mean, measured by the I2C peripheral and that the SCL frequency vary according to the measured rise time? On our opinion, the bus capacitance associated to pullup value should affect the SCL waveform, eventuelly leading to malfunction of rise time is two long but the overall frequency should not change. The I2C block diagram of the reference manual does not show any kind of rise time feeback like a comparator of else. So what ? Does the I2C peripheral implement a kind of rise time measurement of SCL ? Can somebody has experience relative to this issue ? Is there a document with a more detailed explanation on how works the I2C peripheral of the F303 devices ? And finally the important question : assuming that rise time is highly variable in our application, is there a way to configure I2C peripheral to obtain a precise and fixed SCL frequency ? Thanks for your help, Regards, Philippe. #i2c

[Tesla DeLorean]

Posted on October 12, 2016 at 19:33

The pins are configured open-drain, the chip has no active role in the rise time.

Are you using the HSI clock, have you looked at the rate of that internal clock vs the significantly off frequency you report? Could you perhaps express it as a % of requested clock, and does it scale with frequency?

[philippe239955_stm1_stmicro_co]

Posted on October 13, 2016 at 08:02

Hi Clive,

To avoid HSI accuracy issue, we have done the SCL measurement using HSE (30ppm accuracy) as PLL input to generate system clock. The SCL frequency for 400kHz for example varies from 345kHz to 440kHz. This is far more than the HSE accuracy. On your opinion, there is no feedback on SCL regarding the effective rise time of the signal ? At least, when using clock stretching, it is obvious that the master has a feedback on SCL to check if the slave holds SCL low. So, there is clearly a feedback, even if SCL output pin is open drain. Moreover, I don't understand why, in the reference manual and in AN4235, the SCL clock period formula is Tscl = Tf + Tlow + Tr +Thigh; with Tr defined as a function of the effective Rp and Cb that are pullup resistor and I2C bus capacitance. These two values are those physically presents on the bus. They should not affect the frequency but the waveform shape leading to shorter low time and high time when Tr and Tf increase.

[philippe239955_stm1_stmicro_co]

Posted on October 13, 2016 at 13:56

Well, I got it !

I did not read enough the reference manual. In RM0316 §28.4.8 page 844, it is clearly stated that there is a clock synchronization mechanism taking care of SCL rise and fall times. As a consequence, it is possible to achieve I2C fixed clock frequencies on an I2C bus only if the rise and fall time are constants. The SCL output is open drain so it is not an issue for fall time. Regarding rise time, it is a function of the bus capacitance and the pullup value. If they are both constants, rise time is constant. However, our application is a kind of USB-to-I2C bridge and we cannot control what is connected on the I2C bus. As a consequence, fall time is not constant and therefore we cannot ensure a fixed SCL frequency; only a nominal one that will vary according to effective rise time. I have made frequency measurements with pullup resistors of 1K, 3K3, 10K and 47K pullup with a constant bus capacitance and the measurements clearly show a frequency decrease while resistor pullup increase (and then rising time increase). Topic is closed.