STM32F207 FSMC connected to especially device

kruzicka · ‎2014-05-14

Posted on May 14, 2014 at 11:53

I have a question about connecting specially device to a FSMC interface on STM32F207IGT6. There is some points describing this case it bellow.

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MCU: STM32F207IGT6

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DEVICE: MVBCS1 – Siemens ASIC

Shared SRAM 1MB, data 16bit

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Interface: FSMC (STM32F207IGT6) <-> MVBCS1

FSMC configure to MVBCS1 connecting:

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NOR FLASH mode

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Synchronous

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24MHz FSMC CLK (must be, require MVBCS1) – 96Mhz AHB CLK/4

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Single burst

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Wait enable

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Wait configuration – waitstate inserted during WAITN active

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WAITN active in logical 1

There are some questions, which are not explained by a STM datasheets.

Main question:

1) Will MCU wait before first issue a data on FSMC in read operation, when WAITN is active.

2) Will MCU wait before first write a data on FSMC, when WAITN is active?

I need, that MCU was waiting (WAITN is active before a data) before a data operation is possible in single burst mode.

There is some timing diagram with explanation this case.

Thanks for a reply

waclawek.jan · ‎2014-05-14

Posted on May 14, 2014 at 12:37

I have no experience with synchronous mode of FSMC, but based on description (e.g. under ''Data latency versus NOR Flash latency, ''Some recent memories assert NWAIT...'') will probably honor the WAIT signal before the first data phase.

But I personally would go for an experiment on some devboard (DISCOVERY or similar), mimicking the WAIT signal from a GPIO or for more sophisticated setup, from a ADV-latched-CLK-driven PISO shift register, or something similar.

JW

troy1818 · ‎2014-05-15

Posted on May 15, 2014 at 10:35

Hi,

I believe that when you have configured Wait pin for FSMC the MCU should wait for this signal to de-assert before doing more FSMC stuff. It seems resonable, but you never know until you try as previous poster pointed out.

/Regards

rygelxvi

kruzicka · ‎2014-05-19

Posted on May 19, 2014 at 15:54

Official answer from ST technical support is possible for this case. NWAIT will be respected by STM32F207, and (depencies on NWAIT setting) inserted waitstate to a DATA - of course in a DATA0 cycle.

Thanks a lot for answers

Karel R.