STM32F1xx: Confusion on CCRx value for a given PWM frequency with TIM1 PWM Output???

[JayD]

I'm using an old STM32F103RD with SPL v3.6.1. I'm confused with the value to put in TIM1_CCRx for a giving PWM frequency.

Looking at \STM32Cube_FW_F1_V1.7.0\Projects\STM32F103RB-Nucleo\Examples_LL\TIM\TIM_PWMOutput\Src\main.c:

 /* Set compare value to half of the counter period (50% duty cycle ) */

 LL_TIM_OC_SetCompareCH1(TIM2, ( (LL_TIM_GetAutoReload(TIM2) + 1 ) / 2));

but I found in slider of STM32F7 webinar (en.STM32F7_WDG_TIMERS_GPTIM.pdf, see screenshot) that we should substract 1.

Ex: ARR = 4999, for a duty cyle of 50%, CCR1 = (4999+1) * 0.5 = 2500 or 2499?

Does the PWM mode (edge vs center-aligned) have an impact CCRx formula?

[Tesla DeLorean · Accepted solution]

>>Ex: ARR = 4999, for a duty cyle of 50%, CCR1 = (4999+1) * 0.5 = 2500 or 2499?

These are things you should be able to readily check with a scope. Would suggest using smaller numbers so the granularity of the difference is obvious.

My understanding of the PWM1 mechanics are:

Where ARR = 4999

CCR1=0 Always Off

CCR1=5000 Always On

CCR1=1250 25%

CCR1=2500 50%

[JayD]

Thank you for the quick answer Clive!

That's what I tought also before seeing "useful formula" slide from STM32F7 webinar which confuse me.

From the reference manual of STM32F10x (see screen capture), there seems to be a slight difference for Always On (100%) between Edge vs Center-Aligned PWM generation.

[Tesla DeLorean]

I'm not doing motor or complex PWM work, so really haven't committed resources to understanding all the facets of the center aligned or up-down modes. I think ST had an App Note or Cook Book type document for the TIM, and the RM should define behaviour that should be reproducible on the bench where there are doubts.

[waclawek.jan]

The issue here is not edge vs. center aligned, but up vs. downcounting. Downcounting shifts the edge by one count, see description of PWM modes in TIMx_CCMR1.OC1M. Center aligned changes direction soon enough that that shift results in the no pulse for CNT=ARR case, presumable for reasons of symmetry.

One consequence of what's said above is also that there's no 0% PWM in edge-aligned downcounting.

JW

[JayD]

Clive's answer is confirmed in AN2580 - STM32F10xxx TIM1 application examples.pdf.

@JW Thank you for the edge vs center aligned clarification.