STM32F103 - Confusing statement in DMA req mapping section 13.3.7, page 281 of RM0008

[Bags]

Being fairly new to the STM32 architecture I find the following statement in the STM32F103 reference manual really confusing ...

"..., this means that only one request must be enabled at a time."

(the same also applies to the DMA2 controller).

I think this statement should read as follows....

"..., this means that only one request can be serviced at a time."

From my understanding (correct me if I am wrong) each DMA channel has its own interrupt vector (and their own addr\counter registers) , so even if every channel on DMA1 was enabled & signaled a request simultaneously the processor would be able to service each request deterministically based on the built-in channel priority order.

[waclawek.jan]

> each DMA channel has its own interrupt vector

I understand what do you want to say but this is incorrectly worded: DMA is *not* an interrupt controller; however, it can generate interrupts on its own, so this just confuses two very different concepts.

It would be more appropriate to say, that there is an arbiter in DMA, which ensures, that only one channels is working at a time (this gets more complicated in the more complex dual-port DMA in 'F4 and up, but holds completely true in the single-port DMA in 'F1).

What those remarks intend to say is, that you must not enable multiple DMA sources for *one* particular DMA channel. For example, for Channel 1, you must not enable both DMA from TIM2_CH3 (i.e. set TIM2_DIER.CC3DE) and TIM4_CH1 (i.e. set TIM4_DIER.CC1DE).

The reason is, that the DMA requests (triggers) for one channel in the 'F1 are simply OR-ed together. In other STM32 families, the request-steering schemes are different.

JW