2011-12-08 10:32 AM
From their respective RMs:
STM32F1... 0x4002 2000 - 0x4002 23FF Flash memory interface STM32F4... 0x4002 2000 - 0x4002 23FF GPIOI Thus a project predicated on STM32x compatibility must have at least different I/O base addresses based on processor type. Damn! I guess I have to say it again, “substantial compatibility� or in ST’s case, “compatible�, means incompatible. Now I have to go through, identify all the differences and come up with a way to select the proper include files. Does anyone know if the (possibly subset of) I/O offset address are always the same?2011-12-08 10:39 AM
The AFIO/Muxing is also completely different.
If you have code dependent on addresses and bits within peripheral registers you'll probably be spending a lot of time reworking it.2011-12-08 12:35 PM
How true. Fortunately it’s “only�? an RTOS. But some H/W setup needs to be done. Example: a millisecond tick.
At least I don’t have much in the way of I/O drivers. But ST said that the F4s were compatible. A binary that works on my STM3210E-EVAL will not work on my new F4 Discovery board. Setting 2 wait states for 72MHz on the older processor sets bits for GPIO port I on the newer processor. Bah, humbug!