Posted on June 24, 2016 at 09:04
Good day!
I have simple SPI read func:
bool SPIRead(byte reg, byte &result)
{
ushort timeoff=0x100;
volatile short temp;
temp=SPI2->DR;// To clear DR
temp=SPI2->DR;
temp=SPI2->DR;
CS_EN;// i still don't understand why ST can't do this in hardware mode.
SPI2->DR=reg|0x80;
busy=true;
while(!(SPI2->SR&SPI_SR_RXNE) && timeoff--);
CS_DIS;
result=SPI2->DR>>8;
busy=false;
return timeoff > 0;
}
This func is called for 50 times per sec (SPI clock = 93750Hz (24MHz AP1B clock/256) ).
I have next problem - when i debug this code (in keil), when i step
SPI2->DR=reg|0x80;
i see in regs FRLVL=2 and RXNE = 1. This is normal - there was 16 clocks and mcu received 16 bits. But in next step (busy = true;) in asm (movs r0,#0x01)
FRLVL cleared and RXNE cleared too. They cleared before i read DR. The datasheet says that:
A read access to the SPIx_DR register must be managed by the RXNE event. This event is triggered when data is stored in RXFIFO and the threshold (defined by FRXTH bit) is reached. When RXNE is cleared, RXFIFO is considered to be empty.
Ie RXNE
bit must
not be cleared
until I
read
register
. It is not mentioned in errata. What i am doing wrong?
Thanks!
