STM32746G RTC problem
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2017-08-09 11:56 PM
Hi Everyone,
I am working on RTC with stm32f746g controller. I tried number of option but i am not getting accurate time.
After some time rtc is getting lag of 4 to 5 seconds and it keep on lagging in time.
I am using 32.768khz exteranl crystal with 24pf capacitors.
I tried by changing this capacitors value 22pf,15pf,10pf also but still my problem is not solved.
I did internal rtc calibration also to minimize this error by changing prescaler values but still i am getting time lag.
Can anyone suggest me any other option which will work out and i will get accurate time?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2017-08-10 04:28 AM
After some time rtc is getting lag of 4 to 5 seconds and it keep on lagging in time.
After what time? When talking about error in measuring real-time, it's customary to give it in ppm = parts per million = (deviation / total elapsed time) * 1,000,000.
With the LSE/32.768kHz crystal, up to 100ppm is relatively normal, 10ppm is what can be achieved with moderate effort. 100ppm converts into cca 8 seconds per day.
JW
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2017-08-10 05:05 AM
Hi
Waclawek.Jan
,In 12 hours i am getting almost 15 minutes time lag. As per formula
(deviation / total elapsed time) * 1,000,000
it is 20833 ppm.
I am using AB38T-768KHZ crystal.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2017-08-10 06:06 AM
Make sure the prescaler/divider values are correct. N-1
There should be a way to benchmark LSE vs HSE or PLL, you should quantify the actual crystal speed, and use that to tweak the calibration, prescaler and divider values. Should also be possible emit LSE via a pin.
Is the crystal in question a 6-7pF one, or a 9 or 12pF one? STM32 parts have historically worked far better with the former.
Up vote any posts that you find helpful, it shows what's working..
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2017-08-10 07:36 AM
That's way too much.
Read out and post the content of RCC_BDCR, RTC_PRER and RTC_CALR.
JW
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2017-08-11 03:10 AM
In RCC_BDCR register LSE_ON & LSE_EN bit is set
i am using LSE as a clock source for RTC (RCC_RTCCLKSOURCE_LSE ).
Configured RTC prescaler values so i should get 1 Hz frequency as mentioned below .
RTC_ASYNCH_PREDIV --> 0x7F
RTC_SYNCH_PREDIV --> 0x00FF(mentioned in a AN4759)
I am using calender feature of rtc to get accurate time and date.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2017-08-11 03:18 AM
Prescaler values are set correctly which is given below.
RTC_ASYNCH_PREDIV --> 0x7F
RTC_SYNCH_PREDIV --> 0x00FF
It is mentioned in ST application note AN4759.
I am using 32.768Khz crystal with load capacitance 12.5pF (digikey part no
535-9034-ND )
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2017-08-11 09:29 AM
Read out and post the WHOLE content of RCC_BDCR, RTC_PRER and RTC_CALR.
JW
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2017-08-11 12:08 PM
Hi
Gopale.Nikhil
‌,I checked your watch crystal pullability which is good from Abracon datasheet. The PPMs you have are not normal. ..
I recommend you the following :
1) Read our exaustive App note
Be patient to the end. I know it is long.
2) First please in Firmware select our highest drive of LSE bits to 0x11 to be ableto match thus crystal :ESR max is 30KOhm which is helping a lot.
3) CL1 =CL2 should be in range of 20pF . I Assumed your Cs =2.5pf bu I need your schematics and PCB layout to do a sanity check. You need to create a local ground loop to isolate PC14 and PC15 from other high speed signals crossing. .. I recommend then to do a tuning using an universal counter and output LSE clock at MCO pin PA8. Please do not use PC13 pin at thus step and avoid toggling it... it may disturb PC14 osc in.
4) tune CL1 and CL2 until you will get a proper PA8 output at 768KHz +/- your PPMs. You can monitor your duty cycle also it should be in range if 40 to 60 %.
5) Do not activate other peripherals. During (3). You can even put the CPU in sleep mode.
6) I m sure you will untersrand and debug what is happening in your case.
Cheers
STOne -32
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2017-08-12 07:23 AM
Hi
,Please check attached schematic and layout of the board. Let me know hardware point of view it is correct or not.
Also tell me how much Cs i should consider while calculating CL1 & CL2 values.Now i am using 24pf Capacitors.
Nikhil
________________ Attachments : layout.pdf : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HyW2&d=%2Fa%2F0X0000000b8s%2F9SOs0U4lN38YCBt8oaUjG64oYkbz70a_9ZqCQTjjwfg&asPdf=falseschematic.pdf : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HyVs&d=%2Fa%2F0X0000000b8t%2FRuMyMU6VXiur6HoB.T2N9V2vdkW3cuIkcUDPz1f0joM&asPdf=false