stm32072xx PLL and clock config

[Gaucho]

Hi,
I'm newbie but I need to check if the second code block includes the first code block.
I'm dealing with stm32F072xx.
If required I can share more part of code.

1:

RCC->CR |= RCC_CR_HSION;
while(!(RCC->CR & RCC_CR_HSIRDY)){};

RCC->CFGR &= ~(RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC);
RCC->CFGR |= (RCC_CFGR_PLLSRC_HSI_DIV2 | PLL_MULT_X12);

/* Turn on the PLL and wait for the hardware to set the ready flag */
RCC->CR |= RCC_CR_PLLON;
while(!(RCC->CR & RCC_CR_PLLRDY)){};

/* Now set the clock source of the system clock */
RCC->CFGR &= ~(RCC_CFGR_SW);
RCC->CFGR |= RCC_CFGR_SW_PLL;
while(!(RCC->CFGR & RCC_CFGR_SWS_PLL)){};

2:

HAL_Init();

RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInit;

// Set up the oscillators
// use internal HSI48 (48 MHz), with PLL
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; //it was RCC_PLL_NONE //added by me
RCC_OscInitStruct.PLL.PLLSource = LL_RCC_PLL_MUL_12; //added by me NOT SURE IF THIS IS CORRECT!!!

// Set sysclk, hclk, and pclk1 source to HSI48 (48 MHz)
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK |
RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI48;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;

// Set USB clock source to HSI48 (48 MHz)
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;

HAL_RCC_OscConfig(&RCC_OscInitStruct);
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1);
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);

HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);

// Enable clock recovery system for internal oscillator
RCC_CRSInitTypeDef RCC_CRSInitStruct;
__HAL_RCC_CRS_CLK_ENABLE();

// Default Synchro Signal division factor (not divided)
RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;

// Set the SYNCSRC[1:0] bits according to CRS_Source value
RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;

// Rising polarity
RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;

// HSI48 is synchronized with USB SOF at 1KHz rate
RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;

// Set the TRIM[5:0] to the default value
RCC_CRSInitStruct.HSI48CalibrationValue = 32;

// Start automatic synchronization
HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);

HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();

[AScha.3]

Hi,

ok, but is there any question , i dont see ?

[Gaucho]

Dear Ascha,

my questions is:

Does the second code block includes the first code block?

[Gaucho]

The two code sections are written in a different way but I suppose they are 2 different methods to set clock and pll. But I’m not sure if the second includes the first one

[AScha.3]

Hi,

ok - but it is permissible to ask why ? You could check it yourself, so is it just some kind of game or ..?

For me , i am using Cube/HAL , setting the clock tree and - fine. finished. Make the program then...

You write "newbe", so why not go an easy way, to move forward ?

[Gaucho]

The reason is that:

1) I’m mixing 2 repos found on GitHub 

2)I’m not using Cube

[Gaucho]

I'm tring to understand it by myself.

The following part seems to use pll with 8mhz input,  divided by2 and multiplied by 12, to obtain 48Mhz, but this part seems to be equivalent to the use of HSI48 to obtain the same result of a 48Mhz:

RCC->CR |= RCC_CR_HSION;
while(!(RCC->CR & RCC_CR_HSIRDY)){};

RCC->CFGR &= ~(RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC);
RCC->CFGR |= (RCC_CFGR_PLLSRC_HSI_DIV2 | PLL_MULT_X12);

/* Turn on the PLL and wait for the hardware to set the ready flag */
RCC->CR |= RCC_CR_PLLON;
while(!(RCC->CR & RCC_CR_PLLRDY)){};

For the second part it is still not clear to me how to convert it to HAL:

/* Now set the clock source of the system clock */
RCC->CFGR &= ~(RCC_CFGR_SW);
RCC->CFGR |= RCC_CFGR_SW_PLL;
while(!(RCC->CFGR & RCC_CFGR_SWS_PLL)){};

[AScha.3]

Good.

To see, what its doing, look at rm , RCC registers:

+

If using HSI at 48M , is same clock, but precision on crystal->HSE->PLL is better . If not needed, can use HSI also.